博碩士論文 etd-0728107-121433 詳細資訊


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姓名 吳佳穎(Chia-Ying Wu) 電子郵件信箱 E-mail 資料不公開
畢業系所 電機工程學系研究所(Electrical Engineering)
畢業學位 碩士(Master) 畢業時期 95學年第2學期
論文名稱(中) CUP產品銲線製程能力改善與分析
論文名稱(英) Process capability improvement and analysis for CUP device
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  • etd-0728107-121433.pdf
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    摘要(中) 在半導體業中成本競爭力是最主要的研發驅動力。單顆的晶片製程成本是直接與它的尺寸成比例的。先進的製程科技縮了小晶片尺寸致使線路活動區縮減,因此銲墊旁的可用區域相對的縮小,而又因在鋁墊下方的區域未完全運用,那是因為在銲線會有之電性傳導失敗之可靠度考量的問題。
    最近許多研究企圖想改善並使用鋁墊下方之空間,因而修改線路之設計之規則,鋁墊下出現有線路通過之結構(CUP)被發展出來。且需求大量的驗證工作來符合可靠度水準。
    CUP(Circuit Under Pad) Device最主要的用意是增加每片晶圓當中的產能,其中有一些是為了線路的安排及測試所特殊設計致使線路跨過鋁墊下。
    本論文是針對CUP Device以實際封裝生產所引發之銲線製程缺點,以銲線製程中所能改善之參數、銲針,及晶圓供應商所提供之晶圓差異,利用JMP/DOE工程手法作驗證分析,改善CUP Device在銲線站之缺點,提升封裝良率。
    摘要(英) Cost competitiveness is a major driving force in the semiconductor industry. The processing cost of an individual die is directly proportional to its size. Advances in processing technology have shrunk the device sizes in wire-bonded chips, resulting in a smaller die core size. However, the space below wire-bond pads remains relatively underutilized because of the reliability concern that electrical loads transmitted during bonding can cause failures in the underlying devices. Recently, studies have attempted to improve the use of space below wire-bond pads. Hence, the circuits under pads (CUP) structure modified layout rules to include circuits structure under pads, was developed, and extensive qualification work is required to meet reliability standards.
    The main purpose of this paper is to investigate the damage caused by the wirebonding process of CUP devices on the in-line assembly packaging manufacture. The root cause of wirebonding failures analyzed were based on the CUP structure and several wire bond parameters; such as bonding force, ultrasonic current, bonding time period, capillary type, machine, and wafer source, which were also confirmed with the DOE/JMP engineer technique. Finally, results were also used to implement the corrective action and the assembly yield of CUP Device has been improved, successfully.
    關鍵字(中)
  • 改善與分析
  • 製程能力
  • CUP產品
  • 關鍵字(英)
  • CUP device
  • improvement and analysis
  • Process capability
  • 論文目次 誌謝.......................................................................................................Ⅰ
    中文摘要...............................................................................................Ⅱ
    英文摘要...............................................................................................Ⅲ
    目錄.........................................................................................................V
    附表目錄................................................................................................VV
    附圖目錄.................................................................................................X
    第一章 序論...........................................................................................1
    1-1 封裝製程之區分........................................................................1
    1-2 釘架產品封裝製程簡易說明....................................................2
    1-3 CUP device 之發展由來及介紹...............................................8
    1-4 Cu/low-k 之介紹......................................................................9
    1-5 研究動機..................................................................................10
    第二章 理論基礎.................................................................................12
    2-1 Wire Bond銲線原理................................................................12
    2-1-1 壓力(Bond Force)作用...................................................12
    2-1-2 能量(Ultrasonic Power)之作用...................................12
    2-1-3 銲線時間(Bond Time)之作用.........................................13
    2-1-4 銲線溫度(Bond Temperature)之作用...........................13
    2-2 參數最佳化...........................................................................13
    2-3 銲針介紹..................................................................................14
    2-4 拉力原理..................................................................................16
    2-4-1斷球頸時之拉力原理.........................................................17
    2-4-2 弧高與拉力強度之關係...................................................17
    2-5 推球原理..................................................................................18
    2-5-1 影響推球強度之因子.......................................................18
    2-5-2 測試理論...........................................................................19
    2-6 彈坑實驗..................................................................................20
    2-6-1 Cratering Test使用材料...............................................20
    2-6-2彈坑測試程序.....................................................................20
    2-6-3 檢驗規範 .........................................................................20
    2-6-4 可能造成彈坑之因素.......................................................21
    2-6-4-1 Test操作方式對cratering 之影響.......................21
    2-6-4-2 材料本身差異...........................................................21
    2-6-4-3.Wire Bonder機台/set-up造成彈坑之因素...........22
    2-7 OPEN/SHORT TEST的原理........................................................22
    2-7-1 O/S分析的目的.................................................................22
    2-7-2 分析O/S REJECT的目的...................................................22
    2-7-3 分析的方法及輔助的設備功能.......................................23
    2-8 可靠度實驗..............................................................................24
    2-8-1 Pre-Condition................................................................24
    2-8-2-1 H.T.S.T.高溫儲存實驗..............................................25
    2-8-2-2 PRESSURE COOKER TEST (PCT)壓力鍋實驗..............25
    2-8-2-3 TEMP. CYCLING TEST 溫度循環實驗........................26
    2-8-2-4 TEMP. HUM. TEST (UNBIAS)溫溼度實驗..................27
    2-8-2-5 Thermal Shock Test 冷熱衝擊實驗........................27
    2-8-2-6 H.A.S.T ( UNBIAS ) 高加速壓力鍋實驗................27
    2-8-3可靠度流程........................................................................28
    第三章 實驗方法與步驟................................................................29
    3-1 實驗流程..................................................................................29
    3-1-1 機台差異實驗......................................................................29
    3-1-2 銲針差異實驗.......................................................................31
    3-2 實驗材料與儀器設備...............................................................37
    3-2-1 實驗材料............................................................................37
    3-2-2 儀器設備............................................................................37
    3-3 實驗操作步驟........................................................................37
    3-4 量測儀器...............................................................................38
    第四章 結果與討論..............................................................................40
    4-1 不同銲線機台之影響...............................................................40
    4-2 不同銲針之影響.......................................................................41
    第五章 結論..........................................................................................41
    參考文獻 [1] Failure Analysis of Wire Bonds. Schafft, Harry A.;Reliability Physics Symposium, 1973. 11th Annual April 1973 Page(s):98 - 104
    [2] Active devices and wiring under chip bond pads: stress simulations and modeling methodology. Awad, E.;Electronic Components and Technology Conference, 2004. Proceedings. 54th Volume 2, 1-4 June 2004 Page(s):1784 - 1787 Vol.2
    [3] 田民波 半導體電子元件構裝技術 五南出版社
    [4] Failure analysis of bond pad metal peeling using FIB and AFM
    Cher Ming Tan; Er, E.; Younan Hua; Chai, V.;Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on [see also Components, Hybrids, and Manufacturing Technology, IEEE Transactions on] Volume 21, Issue 4, Dec. 1998 Page(s):585 – 591
    [5] Active circuits under wire bonding I/O pads in 0.13 μm eight-level Cu metal, FSG low-k inter-metal dielectric CMOS technology Kuo-Yu Chou; Ming-Jer Chen;Electron Device Letters, IEEE Volume 22, Issue 10, Oct. 2001 Page(s):466 - 468
    [6] Comprehensive process design for low-cost chip packaging with circuit-under-pad (CUP) structure in porous-SiOCH film
    Tagami, M.; Ohtake, H.; Abe, M.; Ito, F.; Takeuchi, T.; Ohto, K.; Usami, T.; Suzuki, M.; Suzuki, T.; Sashida, N.; Hayashi, Y.;6-8 June 2005 Page(s):12 - 14
    [7] Backside failure analysis and case studies for Cu/low k technology Huixian Wu; Cargo, J.; 5-8 July 2004 Page(s):127 - 134
    口試委員
  • 許渭州 - 召集委員
  • 廖志雄 - 委員
  • 翁?皒q - 指導教授
  • 口試日期 2007-07-20 繳交日期 2007-07-28

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