||J.L. Hennessy and D.A. Paterson, Computer Architecture A Quantitative Approach, Morgan Kaufman Publishers, Inc., 1990.|
D.J. Lilia, “Reducing The Branch Penalty in Pipelined Processors,” IEEE Computer Magazine, pp: 47-55, July 1988.
S. McFarling, J.L. Hennessy, “Reducing The Cost of Branches,” Proceeding of 13th Annual International Symposium on Computer Architecture, pp: 396-403, June 1986.
N.P. Jouppi, D.W. Wall, “Available Instruction-Level Parallelism for Superscalar and Superpipelined Machine,” The 3rd Int. Symposium on ASPLO, pp: 272-282, April 1989.
M. Johnson, Superscalar Microprocessor Design, PTR Prentice Hill, Inc. 1991.
A.M. Gonzalez, “A Survey of Branch Techniques in Pipelined Processors,” Microprocessing and Microprogramming, pp: 243-257 Vol. 36, 1993.
C.C. Lee, “Optimizing High Performance Dynamic Branch Predictors”, PhD. Dissertation, The University of Michigan, Ann Arbor, 1998.
J.E. Smith, “A Study of Branch Prediction Strategies”, Proceeding of 8th Symposium on Computer Architecture, pp: 135-148, May 1984.
T.R. Gross and J.L. Hennessy, “Optimizing Delayed Branches”, Proceeding of 15th Annual Workshop on Microprogramming, ACM SIGMICRO, pp: 114-120, October 1982.
Control Data 7600 Hardware Reference Manual 60367200, Control Data, Arden Hill, Minn., 1975.
J.Y. Yamour, “Instruction Scan for an Early Resolution of a Branch Instruction”, IBM Technical Disclosure Bull., Vol. 23, No. 6, pp: 2600-2604, November 1980.
P. Chow and M. Horowitz, “Architectural Tradeoffs in The Design of MIPS-X”, Proceeding of 14th Annual International Symposium on Computer Architecture, pp: 300-308, June 1987.
K.F. Lee and A.J. Smith, “Branch Prediction Strategies and Branch Target Buffer Design”, IEEE Transaction on Computer, pp: 6-22, January 1984.
T.Y. Yeh and Y.N. Patt, “A Comparison of Dynamic Branch Predictors That Use Two Levels of Branch History”, Proceeding of the 20th Annual International Symposium on Computer Architecture, pp: 257-266, 1993.
C. Young, N. Gloy and M. D. Smith. “A Comparative Analysis of Schemes for Correlated Branch Prediction”, Proceedings of The 22th Annual International Symposium on Computer Architecture, pp. 276-286, 1995.
A. R. Talcott, M. Nemirovsky and R. C. Wood, “The Influence of Branch Prediction Table Interference on Branch Prediction Scheme Performance”, International Conference on Parallel Architectures and Compilation Techniques, 1995.
P.Y. Chang, E. Hao, T. Y. Yeh and Y. N. Patt, “Branch Classification: A New Mechanism for Improving Branch Predictor Performance”, Proceedings of The 27th Annual AACM/IEEE International Symposium on Microarchitecture, pp: 22-31, 1994.
S. McFarling, “Combining Branch Predictors”, Technical Report TN-36, Digital Western Research Laboratory, June 1993.
P. Y. Chang, M. Evers, and Y. N. Patt, “Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference”, IEEE Proceedings of PACT ’96, pp: 48-57, 1996.
A. Riseman and C.C. Foster, “The Inhibition of Potential Parallelism by Conditional Jumps”, IEEE Transactions on Computer, Vol. C-12, pp: 1405-1411, December 1972.
W. Chu, S. Vassiliadis, J.G. Delgado-Frias, “The Multi-Associative Branch Target Buffer: A Cost Effective BTB Mechanism”, Microprocessing And Microprogramming 41, pp: 211-225, 1995.
H. Perleberg and A.J. Smith, “Branch Target Buffer Design and Optimization”, IEEE Transaction on Computer, Vol. 42, No. 4, pp: 396-412, April 1993.
J. Smith, “A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Main Memory”, IEEE Transactions on Software Engineer, pp: 121-130, March 1978.
G. Cragon, Branch Strategy Taxonomy and Performance Models, IEEE Computer Society Press.
T. Pan, K. So and J.T. Rahmeh, “Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation”, Proceedings of 5th Annual International Conference of Architecture Support for Programming Languages and Operation Systems, pp: 76-84, October 1992.
R. Talcott, W. Yamamoto, M.J. Serrano, R.C. Wood and M. Nemirovsky, “The Impact of Unresolved Branches on Branch Prediction Scheme Performance”, IEEE Transaction on Computer, pp: 12-21, 1994.