本論文主要可分為兩個部分。第一部分(第二章)，我們利用交叉電容耦合對、電感退化及T形諧振電路技術設計本章差動對低雜訊放大器。利用外加T形諧振電路在不增加功率消耗的情況下，提升功率增益及CMRR特性。第一次晶片下線結果，整體晶片面積為0.94 mm*0.914 mm = 0.86 mm2。在操作頻率設計在5.8 GHz下，功率增益為1.76 dB，S11為-22.3 dB，S22為-1.73 dB，在線性度的表現上，IIP3為-9 dBm，IP1dB為-13.2 dBm。第二次晶片下線結果，整體晶片面積為0.94 mm * 0.914 mm = 0.86 mm2。在操作頻率設計在5.8 GHz下，功率增益為7.05dB，雜訊指數為3.54 dB，S11為-40.049 dB，S22為-2.031 dB，在線性度的表現上，IIP3為-8.3 dBm，IP1dB為-13.2 dBm。第二部分(第三章)，我們利用交叉耦合對、LC Tank以及尾端LC Tank來設計運用在5 GHz頻段之低功耗壓控振盪器。此壓控振盪器量測結果，在5.2 GHz相位雜訊在距離輸出振盪頻率1 MHz處為-113.8 dBc/Hz，整體協調範圍達20.3%的頻寬(5.185~6.35 GHz)，整體晶片面積為0.684 mm2，壓控振盪器消耗功率為3.96 mW，而晶片特性則可達到-188.3 dBc/Hz。第四章為總結及未來工作。

This thesis includes two major parts. The first part (in Chapter II), we used cross coupled capacitor, inductive degeneration, and a T-shaped resonant circuit to design a low voltage differential Low Noise Amplifier. In order to enhance the gain and CMRR without increasing additional power on the circuits, the T-shaped resonant circuit plays an important role. The first results of the chip were designed at 5.8 GHz and the chip size was 0.94 mm*0.914 mm = 0.86 mm2. The power gain was 1.76 dB. The S11 was -22.3 dB and the S22 was -1.73 dB. The IIP3 was -9 dBm and IP1dB was -13.2 dBm. The second results of chip were designed at 5.8 GHz and the same frequency band, and the chip size is the same, too. The power gain was 7.05 dB and the NF was 3.54 dB. The S11 was -40.05 dB and the S22 was -2.031 dB. The IIP3 was -8.3 dBm and IP1dB was -17.3 dBm. The second part (in Chapter III), we used cross-coupled, LC Tank, and tail LC Tank to design 5 GHz band low power consumption Voltage Controlled Oscillator(VCO). The VCO can achieve a phase noise of -113.8 dBc/Hz at 5.2 GHz @1 MHz offset across the whole frequency range. Wide tuning range VCO of 20.3% (5.185~6.35 GHz) suitable for tuner application, was obtained. The chip area was 0.684 mm2, and power consumption was 3.96 mW. This VCO work achieves an FOM of -188.3 dBc/Hz. In Chapter IV, the conclusions and future work was described.

目錄
論文審定書 i
誌謝 ii
摘要 iv
Abstract v
目錄 vi
圖表目錄 viii
第一章 導論 1
1.1 研究背景 1
1.2 研究動機 3
1.3 論文組織 3
第二章 5.8GHz高增益低功耗高抑制共模增益之低雜訊放大器 4
2.1 低雜訊放大器概述 4
2.2 重要參數與MOSFET元件雜訊 5
2.2.1 雜訊指數 5
2.2.2 元件雜訊 7
2.2.3 線性度 10
2.2.4 動態範圍 12
2.2.5 穩定度 12
2.3 常用於低雜訊放大器架構 15
2.3.1 輸入阻抗匹配架構 15
2.3.2低功率消耗架構 19
2.4 電路設計 21
2.4.1 增益提升設計 22
2.4.2 提升共模雜訊抑制之設計 24
2.5 量測結果與結論分析 25
2.5.1 第一次下線晶片 25
2.5.2 第二次下線晶片 30
2.6 結語 35
第三章 寬頻低功耗壓控振盪器 38
3.1 壓控振盪器概述 38
3.1.1 振盪原理 39
3.1.2 振盪器架構 40
3.2 VCO之重要參數 43
3.2.1 相位雜訊 43
3.2.2 相位雜訊對通訊系統的影響 49
3.2.3 偏壓點設計 50
3.2.4 振盪器Q值 51
3.2.5 調諧範圍 52
3.2.6 輸出緩衝器 53
3.3 常用之壓控振盪器架構 54
3.3.1 主動埠架構 54
3.3.2 改善相位雜訊之技術 56
3.3.3 提升調諧範圍之技術 58
3.4 壓控振盪器設計 60
3.5 模擬與量測結果比較 61
3.6 結語 66
第四章 結論 67
參考文獻 69

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