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博碩士論文 etd-0013117-100446 詳細資訊
Title page for etd-0013117-100446
論文名稱
Title
具有擴充編碼之高速十二位元數位類比轉換器
A High speed 12-bit Digital-to-Analog Converter with the extended encoding scheme
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
40
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2016-08-25
繳交日期
Date of Submission
2017-01-24
關鍵字
Keywords
數位類比轉換器、高線性度、高速度
DAC, high speed, high precision
統計
Statistics
本論文已被瀏覽 5722 次,被下載 42
The thesis/dissertation has been browsed 5722 times, has been downloaded 42 times.
中文摘要
在行動通訊應用中,數位類比轉換器需要越來越高的精準度和速度。然而行動裝置的使用時間是由電池的容量所限制。提高速度和精準度都是現在數位類比轉換器電路設計的趨勢。由於傳統電流源式架構在高速應用中會因為切換次數過多造成線性度不佳以至於影響動態效能。因此,本文提出新的編碼方式來設計電流導引式架構來設計數位類比轉換器,以實現高速應用。此論文主要架構提出八位元溫度計碼及四位元擴充編碼器的數位類比轉換器之技術,此技術可以減少單一切換次數,讓電路可以有更好的線性度以提高動態效能。
最後,此設計採用TSMC 90nm製程製作。此數位類比轉換器的取樣速率和解析度分別為1GS/s和12位元。功率消耗為27.5毫瓦。模擬結果顯示,所提出的編碼技術,可以提高整體線性度及動態效能。
Abstract
In the mobile communication applications, the Digital-to-analog converter (DAC) needs the higher accuracy and speed. However, the operation time is limited by the battery capacity of the mobile devices. Increasing speed and accuracy are the trend of the current DAC’s circuit design. In the conventional current source architecture of the high-speed applications, the limited dynamic linearity is affected by the excessive number of switches. Therefore, this thesis proposes a new coding method to design a current-steering architecture that the digital-to-analog converter can achieve a high-speed operation for different applications. The proposed DAC architecture is composed of an eight-bit thermometer code and a four-bit expanded encoder digital-to-analog converter. It mainly can reduce the number of times of a single switch. Hence, the circuit can achieve a better linearity to improve the dynamic performance.
Finally, the design was designed in TSMC 90nm CMOS process. The sample rate and resolution of the DAC are 1GS/s and 12-bit, respectively. The power consumption is 27.5mW.
目次 Table of Contents
目錄
Chapter 1 緒論……………………………………………………………1
1.1 研究動機與目標……………………………………………………...1
1.2 論文章節組織……………………………………………………….. 2
Chapter 2 電流源式數位類比轉換器介紹………………………………3
2.1 數位類比轉換器介紹………………………………………………...3
2.2 數位類比轉換器的規格……………………………………………...3
2.2.1 靜態效能(Static Performance)…………………………………. 5
2.2.2 動態性能(Dynamic Performance)……………………………… 5
2.3 電流源式數位類比轉換器 (Current-steering DAC)……………….6
2.3.1 二進制加權數位類比轉換器(Binary-Weighted DAC)……… 6
2.3.2 溫度計碼數位類比轉換器(Thermometer-code DAC)………. 8
2.3.3 分段式數位類比轉換器(Segmented DAC)………………… 10
Chapter 3 應用於 12 位元 1GS/s 擴充編碼式 DAC .......................12
3.1 8 位元溫度計碼結合 4 位元二進制碼的分段式 DAC..................12
3.2 8 位元溫度計碼結合 4 位元擴充編碼的分段式 DAC..................15
3.3 電流單元的數位電路介紹 ......................................................18
3.4 電流單元的類比電路介紹……………………………………… 20
3.5 偏壓電路電路介紹…………………………………………………..21
3.6 單一電流源電路介紹……………………………………………….23
3.7 擴充編碼電流單元…………………………………………………..24
3.8 電路佈局(Layout)…………………………………………………...24
Chapter 4 模擬結果分析............................................................ 26
Chapter 5 結論與未來展望 .........................................................30
5.1 結論…………………………………………………………………..30
5.2 未來展望……………………………………………………………..30
參考文獻 ..................................................................................31
參考文獻 References
參考文獻
[1] R. J. v. d. Plassche, CMOS integrated analog-to-digital and digital-to-analog converters, 2nd ed. Boston: Kluwer Academic Publishers, 2003.
[2] C. Shi and M. Ismail, Data converters for wireless standards. Boston: Kluwer Academic Publishers, 2002.
[3] F. Maloberti and SpringerLink (Online service). (2007). Data Converters. Available: http://dx.doi.org/10.1007/978-0-387-32486-9
[4] B. Razavi, Principles of data conversion system design. New York: IEEE Press, 1995.
[5] R. J. Baker. (2010). CMOS : circuit design, layout, and simulation (3rd ed.). Available: http://onlinelibrary.wiley.com/book/10.1002/9780470891179
[6] R. J. v. d. Plassche, CMOS integrated analog-to-digital and digital-to-analog converters, 2nd ed. Boston: Kluwer Academic Publishers, 2003. [7] K. C. Kuo and C. W. Wu, “A Switching Sequence for Linear Gradient Error Compensation in the DAC Design,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 8, pp. 502–506, August 2011.
[8] Young-Deuk Jeon, Jong-Kee Kwon, ETRI “A 6b 1.4GS/s 11.9mW 0.11mm2 65nm CMOS DAC With a 2-D INL Bounded Switching Scheme”, 2010 SoC Design Conference (ISOCC), 2010 International Papers, pp.198–200, 2010.
[9] C. H. Lin and K. Bult, “A 10-b 500-MSample/s CMOS DAC in 0.6-mm2 , ” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, December 1998.
[10] Y. Cong and R. L. Geiger, “Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, vol. 47, no. 7, pp. 585-595, July 2000.
[11] J. Deveugele, G. Van der Plas, M. Steyaert, G. Gielen, and W. Sansen,
“A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC,” IEEE Transactions on Circuits and Systems Regular Papers
, vol. 51, no. 1, pp. 191-195, January 2004.
[12] C. H. Lin and K. Bult, "A 10-b, 500-MSample/s CMOS DAC in 0.6 mm(2)," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948-1958, Dec 1998.
[13] T. H. Kuo and W. T. Lin, “A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection,” IEEE Journal Solid-State Circuits, vol. 47, no. 2, pp. 444-453, February 2012.
[14] W. H. Tseng, J. T. Wu, and Y. C. Chu, “A CMOS 8-bit 1.6-GS/s DAC with digital random return-to-zero,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 1, pp. 1-5, January 2011.
[15] W. H. Tseng, C. W. Fan, and J. T. Wu, “A 12 b 1.25GS/s DAC in 90 m CMOS with > 70 dB SFDR up to 500 MHz,” in IEEE International Solid-State Circuits Conference, pp. 192–193, 2011.
[16] W. T. Lin and T. H. Kuo, “A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over Entire Nyquist Bandwidth,” 2013 IEEE Solid-State Circuits Conference, Digest of Technical Papers, pp. 474-475, February 2013.
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