階層包圍體(BVH)之樹狀結構是動態場景基於即時光線追蹤繪製的一個非常重要議題，如何透過圖形處理器(GPU)或專用電路來加速這個過程，近年來已經受到了許多關注。為了進一步達到加速建構，本論文擴展了先前學術發展的建構器之設計，建構的運作核心是將一個節點劃分為兩個子節點，並同時決定出子節點下一次分割位置。
本論文的主要貢獻之一是提出一種高效率的並行分群架構，可以同時對同一節點的數個三角形進行分群，並將分群結果均勻分佈在不同的處理單元中，以實現負載平衡。由於並行處理多個三角形，增加了新的分類盒減少(bin-reduction)單元對屬於相同分類盒的三角形做合併化簡。本論文亦增加分割候選位置取樣數，由原先7個增加至15個，以便獲取更高品質的樹狀結構。為了支援更多的分割候選位置取樣和三角形分群能力，擴展了諸如邊界產生單元、分類裁定單元等相關模組的設計，以便增加它們的處理吞吐量。關鍵的後端單元表面積啟發式(SAH)計算也被修改，使得計算週期從102減少到47。
本論文提出的樹狀結構建構器電路硬體成本約2.18M個邏輯閘，並且在90nm製程下可以運行至286 MHz工作時脈。模擬結果表明本論文的樹狀結構建構器可以實現近似文獻的建設時間，僅只需要文獻電路面積的四分之一。本論文所提出的設計可以有助於嵌入式即時光線追蹤系統的開發。

Bounding volume hierarchy (BVH) tree construction is a very important issue for real-time ray-tracing rendering of dynamic scenes. How to accelerate this process by either graphics processor units (GPU) or dedicated circuits has attracted a lot of attention in recent years. This thesis extends one of the previous tree builder designs in order to achieve further speed-up. The core operation of the tree builder is to partition one node into two child nodes, and determine their split locations at the same time. One of the main contributions of this thesis is to propose an efficient parallel partition architecture, which can partition several triangles of the same node simultaneously, and distribute the partitioned results evenly into different processing units to achieve load balance. Because multiple triangles are processed in parallel, a new bin-reduction unit has been added to merge the binning results of those triangles belonging to the same bins. This thesis also increases the candidate split locations from seven to 15 in order to increase the resulted tree quality. In order to support more candidate splits and partitioning triangles, the design of relevant modules such as bin-border-generation unit, bin unit, have been unfolded in order to increase their processing throughput. The key backend units for Surface Area Heuristic(SAH) calculation are also modified such that the calculation cycle is reduced from 102 to 47. The proposed tree-builder costs about 2.18 M gates, and can run up to 286 MHz for 90nm technology. Our simulation results show that the proposed tree builder can achieve the similar building time to the literature but at only about one quarter of the circuit area. The proposed design can contribute to the development of embedded real-time ray-tracing systems.

論文審定書 i
論文公開授權書 ii
摘 要 iii
Abstract iv
目 錄 v
圖 次 vii
表 次 ix
第一章 概論 1
1.1研究動機 1
1.2論文大綱 2
第二章 研究背景與相關研究 3
2.1光線追蹤Ray Tracing 3
2.2 Bounding Volume Hierarchy(BVH) 4
2.3 Surface Area Heuristic 6
2.4 BVH結構與相關變形 7
2.5使用GPU進行分群結構建構 8
2.6光線追蹤ASIC硬體 10
第三章 BVH建構器分析 11
3.1三角形分群 11
3.1.1 Ping-pong Buffer策略 12
3.1.2 Dual Primitive Buffer策略 13
3.1.3不同分群策略之比較 15
3.2 BVH建構器介紹 17
3.3文獻[3]BVH建構器效能分析 19
第四章 BVH樹狀結構建構器的設計 22
4.1三角形分群處理(Partition Process) 25
4.1.1 三角形分群單元(Partition Unit) 25
4.1.2 Buffer讀寫排程 27
4.1.3負載平衡 35
4.2三角形分類處理(Binning Process) 36
4.2.1 邊界產生單元(Bin Border Generation Unit) 36
4.2.2分類裁定單元(Bin Decision Unit) 37
4.2.3分類化簡單元(Bin Reduction Unit) 40
4.3 SAH 計算處理(SAH Calculation Process) 41
4.3.1分群組合單元(Bin Combine Unit) 41
4.3.2 SAH Cost計算單元與SAH Cost比較單元 43
第五章 實作結果與數據比較 46
5.1 RTL模擬環境 46
5.2 場景繪製驗證 47
5.3 實驗結果與數據比較 49
第六章 結論與未來目標 54
參考文獻 56

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