在3GPP-LTE通訊系統標準當中，定義了許多不同長度的快速傅立葉轉換規格，因此我們設計一套獨立且高效能的硬體架構，充分利用模組化的設計概念，達到每級模組之間能夠簡單連接的特性，快速支援多種點數長度的運算功能，使得整體系統架構更符合需求與實用性。
本設計在四級模組情況下，整體系統可執行2~2187點等48種不同長度的運算，其中還包含了32種長度是定義在3GPP-LTE的規格中。然而每一級模組中包含了兩個部分：(1) 多模式可重置式運算核心：以Radix-32和Radix-23為設計基礎，妥善發揮硬體重覆使用的概念，並且在不額外增加任何主要硬體(例如乘法器和加法器)的前提之下，可執行六種不同基底的核心運算。(2) 可重置式先進先出暫存元件：透過系統化之先進先出暫存器排列的設計方法，妥善規劃儲存單元的配置，將硬體的使用率發揮到最大。另外我們針對旋轉因子的部分提出了雙階段旋轉因子產生法，面對多種運算長度的情況下，此技術可讓系統有效地降低面積成本，進一步符合行動通訊系統的需求。
在晶片實現上，利用TSMC-40nm CMOS製程技術，核心晶片面積只為0.318mm2，最高操作頻率為350MHz，其對應的平均功率消耗為44.2mW。相較於目前文獻上的其他架構，我們擁有較好的效能，並且可支援最多快速傅立葉轉換模式的選擇。更重要的是，所提出來的硬體架構設計，擁有較好的可擴充性，在面對尚未定義出規格的第五世代通訊協定，未來僅需透過模組之間快速且簡單地連接，即可符合各種點數長度的需求。

In the 3GPP-LTE communication standard, it defines many kinds of Fast Fourier Transform(FFT) sizes. So, we design a high performance FFT architecture which makes good use of modular design construction and reconfigurable design to achieve easily connection between every 2 stages. This design can be suitable for any requirement.
In the 4-stage module, it can support 48 modes which perform 2-2187 FFT points. It also supports 32 modes defined in 3GPP-LTE communication standard. Each module contains two parts. (1) Reconfigurable Computing Kernel(RC-CK)：We employ radix-32 and radix-23 bases and suitably utilize the hardware reuse property. Without extra of hardware resource (ex：multipliers or adders), it can execute six types of different radix of FFT kernel operations. (2) Reconfigurable First-in First-Out(RC-FIFO)：We develop a high efficient design method for supporting many FFT points. The FIFO plan is easily managed and suitably located to maximize the hardware storage usage. In addition, we propose Section-based Twiddle Factor Generator(STFG) to support multi-FFT points. It can reduce the area cost and satisfy any communication systems effectively.
In the chip implementation, the core area is only 0.318 mm2 by using TSMC 40-nm CMOS technology. The maximal operating frequency is 350 MHz and power dissipation in average is 44.2 mW. As compared with other state-of-the-arts, our proposed work has the best performance and support many FFT points. Most important of all, the proposed hardware architecture has the better scalability. In the future, we can support the undefined specifications of the 5th generation wireless system only by increasing/decreasing the module.

論文審定書………………………………………………………..i
致謝 ……………………………………………………………….ii
摘要………………………………………………………………..iii
Abstract …………………………………………………………iv
目錄………………………………………………………………..v
圖次………………………………………………………………..vii
表次 ………………………………………………………………..ix
第一章 緒論 ……………………………………………………1
1.1 背景 ………………………………………………………....1
1.2 動機與設計目標.......………………………………………..1
1.3 論文架構 ……………………………………………………2
第二章 傅立葉轉換介紹.......………………………………….4
2.1 離散傅立葉轉換與反離散傅立葉轉換….......……………..4
2.2 快速傅立葉轉換........……………………………………….5
2.3 單迴路延遲回授架構..……..………………………………..7
2.3.1 Radix-2、Radix-4與Radix-8的演算法與架構......…..7
2.3.2 Radix-3的演算法與架構……………………………..10
2.3.3 延伸Radix-22與Radix-23的演算法與架構…..……..11
2.3.4 比較各種基數的硬體使用狀況 ……………….……..13
第三章 Radix-rk演算法推導與分析…………………………..14
3.1 Radix-r2演算法介紹………………………………………...14
3.2 Radix-rk優勢分析........……………………………………...16
第四章 新提出的硬體架構....…………………………………..18
4.1 系統簡介.……………………………………………………..18
4.1.1 模組化可重置式之想法與實現....……………………..18
4.1.2 主架構介紹……………….……………………………..19
4.2 技術一:多模式可重置式運算核心.....………………………..22
4.2.1 技術介紹 ………………………………………………..22
4.2.2 電路架構 ………………………………………………..24
4.2.3 效能分析 ………………………………………………..26
4.3 技術二:系統化之先進先出暫存器排列方法.....……………..28
4.3.1 問題陳述 ………………………………………………..28
4.3.2 技術架構簡介與分析…………………….........………..28
4.4 技術三:雙階段旋轉因子產生法…………………….....……..32
4.4.1 設計想法..………………………………………………..32
4.4.2 硬體架構..………………………………………………..35
4.4.3 效能分析.........…………………………………………..37
4.4.4 硬體實現結果..…………………………………………..45
第五章 晶片實現..………………………………………………..48
5.1 合成結果分析...………………………………………………..49
5.2 晶片測試電路結果...…………………………………………..50
5.3 自動測試圖樣產生系統之結果...……………………………..51
5.4 系統佈局成果…………………………………………….........51
5.5 效能比較………………………………………………………..53
第六章 結論與未來展望…………………………………………..56
6.1 結論 ……………………………………………………………..56
6.2 未來展望………………………………………………….……..56

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