在行動通訊應用中，數位類比轉換器需要越來越高的精準度和速度。然而行動裝置的使用時間是由電池的容量所限制。提高速度和精準度都是現在數位類比轉換器電路設計的趨勢。為了增加操作時間，降低數位類比轉換器的功耗是無法避免的。也因此高速度和低功率消耗的數位類比轉換器是具強烈需求的。
由於電流導引式架構在高速應用中有良好的線性，經常被廣泛的應用於高速數位類比轉換器之中。因此，本文採用電流導引式架構來設計數位類比轉換器，以實現高速應用。此論文亦提出溫度計碼數位類比轉換器之省電技術，此技術可以減少功率消耗和時脈訊號貫穿。傳統的設計是在每一個週期使用時脈訊號更新所有電流單元。但此論文的設計是先偵測資料的變化，才更新實際上資料有變化的電流單元。此設計可以節省由閂鎖電路開關所產生的電力消耗。
最後，此設計採用TSMC 90nm製程製作。此數位類比轉換器的取樣速率和解析度分別為1GS/s和12位元。功率消耗為30毫瓦。模擬結果顯示，所提出的省電技術，可以節省電力消耗。即使在最差的情況下，此技術依然可節省10%的耗電量。

In the mobile communication applications, the Digital-to-analog convert (DAC) needs higher and higher accuracy and speed. However, the operation time is limited by the battery capacity of the mobile devices. Increasing speed and accuracy are the trend of present DAC’s circuit design. To increase the operation time, reducing the power consumption of the DAC are necessary. As a result, the high speed and the low power consumption DACs are in high demand.
The current-steering architecture is widely used in high-speed DACs, since this architecture has good linearity at high speed. Therefore, this thesis adopts the current-steering architecture to design the DAC in order to achieve the high-speed application. The power saving technology for the thermometer-code DAC is proposed in the thesis. This technique can reduce the power consumption and the clock feedthrough. Instead of the traditional design, which using clock signal to update all current cells in each period, this design detects the data variation first and then only update the current cells which actually change the data. The proposed design can save the power consumption produced by the latches switched.
Finally, the design was fabricated in TSMC 90nm CMOS process. The sample rate and resolution of the DAC are 1GS/s and 12-bit, respectively. The power consumption is 30mW. The simulation results show that the proposed power saving technology can save power consumption. Even in the worst case, this technique can still save 10% power consumption.

Contents
摘要 III
ABSTRACT IV
CONTENTS V
LIST OF TABLES VII
LIST OF FIGURES VIII
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 3
CHAPTER 2 SURVEY OF CURRENT-STEERING DAC 5
2.1 Introduction 5
2.2 DAC Specification 5
2.2.1 Static Specification 8
2.2.2 Dynamic Specification 10
2.3 Current-steering DAC 12
2.3.1 Binary-Weighted DAC 12
2.3.2 Thermometer-code DAC 14
2.3.3 Segmented DAC 16
2.4 Design Consideration for DACs 20
2.4.1 Cell-Dependent Delay Differences (CDDDs) [29] 20
2.4.2 Output-Dependent Delay Differences (ODDDs) [30] 22
2.4.3 DAC’s Output Impedance and Distortion 24
2.5 Power Saving Technology for DACs 26
2.6 Dynamic Element Matching (DEM) Technique [35] 29
CHAPTER 3 A 12-BIT 1GS/S 90NM DAC 32
3.1 Introduction 32
3.2 Proposed Segmentation DAC Architecture 32
3.3 8-bit Thermometer-Coded DAC 34
3.3.1 Unit Current Cells 34
3.3.2 Column Clock Controller (CCC) 37
3.4 Switching Scheme 40
3.5 4-bit Binary-Weighted DAC 52
3.6 Biasing Circuit 54
3.7 Layout 55
CHAPTER 4 SIMULATION AND EXPERIMENTAL RESULTS 58
4.1 Simulation Results 58
4.2 Measurement Setup 64
4.3 Experimental Results 68
4.4 Summary 70
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS 72
5.1 Conclusion 72
5.2 Future Works 72
REFERENCES 74

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