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博碩士論文 etd-0022114-120427 詳細資訊
Title page for etd-0022114-120427
論文名稱
Title
寬頻帶範圍、無諧波鎖定10-位元全數位連續近似暫存器控制延遲鎖相迴路
A Wide-Range and Harmonic-Free 10-bit SAR All-Digital Delay-Locked Loop
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
65
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2014-01-16
繳交日期
Date of Submission
2014-01-22
關鍵字
Keywords
諧波鎖定、逐次逼近暫存器、延遲鎖相迴路、互補延遲線、解析度
successive approximation register, harmonic locking, resolution, complementary, delay locked loop
統計
Statistics
本論文已被瀏覽 5640 次,被下載 58
The thesis/dissertation has been browsed 5640 times, has been downloaded 58 times.
中文摘要
此延遲鎖相迴路使用TSMC 90nm製程,採用逐次逼近暫存器(successive approximation register, SAR) 以及移位暫存器(shift register)來控制數位延遲線,這樣可以解決諧波鎖定問題並快速鎖定。延遲線的部分採用互補延遲線的方式來提高可鎖定的範圍,並利用粗調及微調的方式來提高延遲的分辨率。此延遲鎖相迴路採用10位元的逐次逼近暫存器來實現快速鎖定。另外,可鎖定的範圍約從100 MHz到1GHz,供應電壓為1.2 V,具有大約4 ps的延遲解析度,在100 MHz功率消耗為0.38 mW、在1 GHz功率消耗為0.9 mW,jitter在100 MHz為8.8ps、1 GHz為2.6ps,鎖定時間在100 MHz為40個時脈週期、1 GHz為24個時脈週期。
Abstract
This delay locked loop uses TSMC 90nm process. It uses the shift-counting type successive approximation register to control the digital delay line, which can solve the problem of harmonic lock. The part of delay line uses a complementary way to improve the range of lockable and using coarse and fine way to improve the resolution of delay. This delay locked loop uses 10-bit successive approximation register to achieve the fast locking. In addition, the locking range is from 100 MHz to 1 GHz. The supply voltage is 1.2V. The delay resolution is about 4 ps. The power is 0.38 mW at 100 MHz and 0.9 mW at 1 GHz. The jitter is 8.8 ps at 100 MHz and 2.6 ps at 1 GHz. The lock time is 40 clock cycles at 100MHz and 24 clock cycles at1 GHz.
目次 Table of Contents
摘要 II
ABSTRACT III
LIST OF TABLES VII
LIST OF FIGURES VIII
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 2
CHAPTER 2 DELAY-LOCKED LOOP BASIC CONCEPTS 3
2.1 Introduction 3
2.2 Skew 3
2.3 Jitter 4
2.3.1 Categories of Jitter 4
2.3.2 Clock Jitter 5
2.4 Lock Range 10
2.4.1 Harmonic Locking 12
2.4.2 Stuck Locking 13
2.5 Phase Detector (PD) 14
2.5.1 Conventional static Phase Detector 15
2.5.2 Dynamic phase detector 16
2.6 Digital Delay Line Controller 17
2.6.1 Register-controlled 17
2.6.2 Counter-controlled 19
2.6.3 SAR-controlled 20
2.7 Digital Delay Line Controller 21
2.7.1 Register Shift Delay Cell 21
2.7.2 Capacitor Shunt Delay Cell 22
2.7.3 Binary-Weighted Delay Cell 23
CHAPTER 3 DIGITAL DELAY-CONTROLLED SAR DLL 25
3.1 Introduction 25
3.2 Proposed Circuit 25
3.3 Phase Detector 27
3.4 Delay-Controlled SCSAR (Shift-Counting type Successive Approximation Register) 32
3.5 Digital Delay Line 37
3.5.1 Coarse Delay Line 37
3.5.2 Fine Delay Line 40
3.6 Other control circuit 40
3.6.1 Clock Select Unit 41
3.6.2 Range Select Unit 41
CHAPTER 4 SIMULATION AND EXPERIMENTAL RESULTS 42
4.1 Simulation of PD 42
4.2 Simulation of SCSAR 43
4.2.1 Simulation of shift search state 43
4.2.2 Simulation of conventional SAR state 44
4.3 Simulation of Delay Line 45
4.4 Simulation of DLL 47
4.5 Simulation of static phase error 48
4.6 Simulation of peak-to peak Jitter 49
4.7 Comparison 50
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS 51
5.1 Conclusion 51
5.2 Future Works 51
REFERENCES 52
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