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博碩士論文 etd-0022114-122004 詳細資訊
Title page for etd-0022114-122004
論文名稱
Title
高速連續漸近式類比數位轉換器設計
High Speed SAR Analog to Digital Converter Design
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
68
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2014-01-16
繳交日期
Date of Submission
2014-01-22
關鍵字
Keywords
靴帶式交換器、動態比較器、低功耗、連續漸近式、類比數位轉換器
Bootstrapped switch, Dynamic Comparator, Successive Approximation, Low power, Analog-to-Digital Converter
統計
Statistics
本論文已被瀏覽 5704 次,被下載 59
The thesis/dissertation has been browsed 5704 times, has been downloaded 59 times.
中文摘要
本論文採用TSMC 90nm製程技術,實做一個8位元,150萬取樣速率類比數位轉換器。採取連續漸近式類比數位轉換器架構之低功耗的優點來達到此的設計目標,其中透過使用動態比較器技術以減少靜態功率消耗,以及非單調性電容陣列切換方法,來降低整體的功率消耗。為達到高速的需求,額外設計一比較器,在電路取樣階段時進行最高位元之轉換,以提高類比數位轉換器的轉換速度;並使用對稱式靴帶式交換器以控制前端取樣開關,進而達到減少低電壓操作時對取樣保持電路線性度的影響。
Abstract
In this thesis, the circuits are designing with TSMC 90nm CMOS process and 1.2V of supply voltage. The speed and resolution of ADC are 8-bit and 150MS/s individually. In order to achieve low power, Successive Approximation ADC has been adopted for the proposed ADC. The comparators in the proposed ADC are dynamic comparators which consume no static power consumption. Capacitor arrays in the proposed ADC are monotonic switching procedure to save much more power consumption. To enhance the sampling rate, an additional comparator for MSB is designed for the ADC using in sample phase. At last, the bootstrapped switch is used for controlling the sampling in the front-end, and it can reduce the impacts of linearity for operating under low supply voltage.
目次 Table of Contents
中文摘要 II
ABSTRACT III
LIST OF TABLES VI
LIST OF FIGURES VII
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 3
CHAPTER 2 OVERVIEW OF ANALOG TO DIGITAL CONVERTER 4
2.1 ADC Performance Specifications[1, 3] 4
2.2 ADC Architecture [1-3] 11
2.2.1 Flash ADC 11
2.2.2 Two-Step Flash ADC 13
2.2.3 Pipelined ADC 14
2.2.4 Successive Approximation ADC 16
2.2.5 Time Interleaved ADC 18
CHAPTER 3 THE PRINCIPLE OF DESIGNING A SAR ADC 20
3.1 Introduction 20
3.2 Switch 20
3.2.1 ON-Resistance 20
3.2.2 Charge-Injection 21
3.2.3 Clock Feedthrough 22
3.3 Sample and Hold Circuit 23
3.4 Comparator 26
3.4.1 Static Latched Comparator 27
3.4.2 Class-AB Latched Comparator 28
3.5.3 Dynamic Latched Comparator 29
3.5 Capacity Array 30
3.5.1 Binary Weighted Capacity Array 31
3.5.2 C-2C Capacitor Array 31
3.5.3 Binary Weighted Array with Monotonic Capacitor Switching 32
CHAPTER 4 IMPLEMENTATION OF SUCCESSIVE APPROXIMATION ADC 34
4.1 CMOS Switch 34
4.1.1 Transmission Gate 35
4.1.2 Bootstrapped Switch 37
4.2 Dynamic Comparator 39
4.3 Additional Comparator for MSB 41
4.4 Capacitor Array 45
4.5 DAC control Logic 48
4.6 SAR Logic 49
4.7 Summary 51
CHAPTER 5 CONCLUSION AND FUTURE WORK 54
5.1 Conclusion 54
5.2 Future Work 54
REFERENCES 56
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