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博碩士論文 etd-0029118-121816 詳細資訊
Title page for etd-0029118-121816
論文名稱
Title
使用正負緣觸發正反器之八位元低功耗移位器
An 8-bit Shift Register Using Double-Edge Triggered Flip-Flops
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
55
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2018-01-15
繳交日期
Date of Submission
2018-01-29
關鍵字
Keywords
全PVT、預佈局模擬、位移寄存器、DETFF、低功耗、佈局模擬
pre-layout simulation, all-PVT, low power, post-layout simulation, shift register, DETFF
統計
Statistics
本論文已被瀏覽 5906 次,被下載 5
The thesis/dissertation has been browsed 5906 times, has been downloaded 5 times.
中文摘要
功率消耗對於IC設計人員已經成為一個重要議題,由於電池壽命有限,功耗被視為電池供電系統 ( 如手機,筆記型電腦等 ) 的重要條件。本文提出一種基於低功耗雙邊緣觸發正反器(DETFF) 的8位元位移寄存器。此研究使用Cadence Virtuoso 5.1版本和TSMC 0.18um 製程,完成基於低功耗DETFF 的8位元位移寄存器。本文提出的設計貢獻在於透過使用雙時脈技術來鎖存數據位元,同時達成更短的時間延遲以及更少的功耗。全PVT角落 ( 製程、電壓、溫度 )佈局後模擬結果顯示,在最高125 MHz時脈頻率下的功率消耗為35.22 mW 。

關鍵字:位移寄存器、DETFF、低功耗、佈局模擬、全PVT, 預佈局模擬
Abstract
The power dissipation has become an essential issue for IC designers, which is considered a primary factor for battery-operated systems, such as a mobile phone, laptop or notebook, and some others digital devices due to the limited battery life. This thesis presents an 8-bit shift register based on a lower-power double-edge triggered (DETFF) flip-flop. In this research, the 8-bit shift register based on the low-power DETFF is carried out by using Cadence Virtuoso version 5.1 and to TSMC 0.18µm CMOS technology. The major contribution of the proposed design is a method using a double-clocking technique to latch data bits such that shorter time delay and the less power dissipation are achieved at the same time. The all-PVT-corner (process, voltage, temperature) post-layout simulation results demonstrates 35.22 mW at the highest 125 MHz clock rate.

Keywords : shift register, DETFF, low power, post-layout simulation, all-PVT
目次 Table of Contents
Table of Contents

Acknowledgement i
Abstract ii
摘要 iii
Table of Contents iv
List of Tables vi
List of Figures vii
Chapter 1 INTRODUCTION 1
1.1 Background 1
1.2 Prior Arts 2
1.3 Motivation of the Thesis 6
1.4 Organization of the Thesis 6
Chapter 2 CIRCUIT DESIGN OF 8-BIT SHIFT REGISTER 8
2.1 Double-Edge Triggered Flip-flop 8
2.2 Inverter Sizing Issue 12
2.3 Shift Register 13
2.4 An 8-bit Shift Register Using DETFF 16
Chapter 3 IMPLEMENTATION and SIMULATION 19
3.1 Schematic Design 19
3.2 Layout Design and Post-layout Simulation 28
3.3 Setup and Hold Time Estimation 33
3.4 Performance Comparison 36
3.5 Summary 37
Chapter 4. CONCLUSION AND FUTURE WORK 38
References 39
參考文獻 References
References
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