此全數位鎖相迴路(All-Digital Phase-Locked Loop，ADPLL)使用TSMC 90nm製程，採用數位頻率偵測器(Digital Frequency Detector，DFD)和連續逼近暫存器(Successive Approximation Register，SAR)與控制單元(Control Unit，CU)以及數位控制振盪器(Digitally Controlled Oscillator，DCO)所組成。
此全數位鎖相迴路具有下列特點:
1. 數位控制振盪器使用低功耗史密特觸發式(Low power Schmitt trigger)反向器作為延遲元件，降低功耗以及減少輸出抖動量。
2. 解析度分成6位元粗調和5位元細調，粗調的延遲時間範圍涵蓋了細調的延遲時間，透過延遲元件給予最低有效位解析度。
3. 使用改良式連續逼近暫存器，可以解決因製程、電壓和溫度的條件無法持續追蹤鎖定而造成全數位鎖相迴路死鎖的問題，讓整個鎖相迴路在鎖定之後能夠持續對電路做追蹤後鎖定。
全數位鎖相迴路電路的工作電壓為1V，鎖相迴路的輸入參考頻率為20MHz，工作頻率範圍為250MHz~1GHz，在1GHz操作下之功率消耗為0.438mW，時脈抖動模擬1GHz為26.7ps。

This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as some control units.
This all-digital phase-locked loop has the following characteristics:
1. The digitally controlled oscillator uses the low power schmitt trigger inverter as a delay element to reduce power consumption and reduce output jitter.
2. Resolution is divided into 6-bit coarse-tuning and 5-bit fine-tuning , coarse delay time range covers the fine delay time, through the delay component to give the least significant bit resolution
3. The use of improved successive approximation register , can solve the process, voltage and temperature conditions can not continue to track the lock caused by all-digital phase-locked loop deadlock problem, so that the entire phase-locked loop after the lock can continue to do the circuit Locked after tracking.
The supply voltage is 1 V. The reference frequency is 20 MHz. The output frequency can achieve from 250 MHz to 1 GHz. The power consumption is 0.438 mW at 1GHz. The simulation of the jitter is 26.7 ps at 1 GHz.

論文審定書 i
中文摘要 ii
ABSTRACT iii
目錄 iv
圖目錄 vi
表目錄 viii
第1章 緒論 1
1.1 研究動機 1
1.2 論文組織架構 2
第2章 鎖相迴路基本觀念 3
2.1 前言 3
2.2 類比鎖相迴路 3
2.3 數位鎖相迴路 7
2.3-1 相位頻率偵測器 8
2.3-2 充電幫浦&迴路濾波器 10
2.3-3 壓控振盪器 12
2.4 全數位鎖相迴路 12
2.5 數位控制振盪器 15
第3章 全數位鎖相迴路設計 18
3.1 系統架構 18
3.2 數位頻率偵測器 19
3.3 粗調連續逼近暫存器 23
3.4 具有持續追蹤功能之微調連續逼近暫存器 25
3.5 數位控制振盪器 27
3.5-1 數位控制振盪器原理與設計 29
3.5-2 延遲元件 30
3.6 除頻器 32
第4章 模擬結果 33
4.1 數位頻率偵測器模擬 33
4.2 粗調連續逼近暫存器模擬 34
4.3 具有持續追蹤功能之微調連續逼近暫存器模擬 35
4.4 數位控制振盪器模擬 36
4.5 除頻器模擬 40
4.6 全電路模擬 41
4.7 時脈抖動模擬(peak-to-peak jitter) 42
4.8 電路規格與比較 42
第5章 結論與未來研究 44
5.1 結論 44
5.2 未來研究 45
參考文獻 46

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