本論文第一個主題提出一種小面積及具省電功能之輸出級電路。此種新式的電路設計利用濾除掉不需要的突波雜訊，能有效地減少晶片電源中主要來自輸出級的功率消耗，但必須稍微的犧牲時脈延遲造成晶片的操作速度。可濾除突波雜訊大小之範圍，主要由數位式選擇開關或熔斷保險絲之方式來達成。根據在晶片上實際的測試結果，當最大操作速度為200 MHz，且輸出電容負載為10 pF時，使用本突波濾波器電路近乎可節省近 28% 之功率消耗。
本論文第二個主題提出一個19-T (19個電晶體)構成之全加法器，此全加法器利用高阻抗電路與衝突電路所設計，由於此方式設計的電路能夠減少使用之電晶體數，進而降低在晶片中所佔的面積及功率消耗。

A novel power-saving and small-area digital output cell is proposed in the first topic of this thesis. The new output cell dramatically reduces the output power consumption by filtering pre-defined spikes, which have been considered as one of the major power dissipation sources of the whole chip, with little sacrifice of speed or delay. The bound of the spikes to be removed can be pre-defined either dynamically by digital selection signals or permanently by fuses to be burned. The maximum operating clock is 200 MHz given a 10 pF off-chip load based on testing result of the testkey chip with an almost 28 % power reduction at all PVT corners.
The second topic presents a design of a 19-T (19 transistors) full adder with high impedance circuit and conflict circuit. The transistor count is dramatically reduced such that the power dissipation as well as the area on chip is very small .

摘要 i
Abstract ii
第一章 簡介 1
1.1 前言 1
1.2 文獻探討 2
1.3 論文目的 4
1.5 論文大綱 5
第二章 具突波濾波之小面積數位輸出電路
6
2.1 簡介 6
2.2 原理說明 7
2.3 電路架構設計 8
2.3.1 整體電路架構 8
2.3.2 正向突波濾波器(PSF)電路 10
2.3.3 負向突波濾波器(NSF)電路 11
2.4 模擬結果 13
2.5 省電效果之規格比較 17
2.6 晶片佈局 18
2.7 測試結果 19
2.8 結論 23



第三章 利用高阻抗邏輯及衝突電路來設計的全加法器電路 24
3.1 簡介 24
3.2 設計原理說明 25
3.3 電路架構設計 27
3.3.1 全加法器之進位電路 28
3.3.2 全加法器之“和”電路 30
3.4 測試考量 33
3.5 模擬結果 33
3.6.1 一位元全加法器之模擬結果 33
3.6.2 八位元全加法器之模擬結果 35
3.6 規格比較 39
3.7 晶片佈局 40
3.8 晶片實測結果討論 42
3.8.1 一位元全加法器之實測結果 43
3.8.2 八位元全加法器之實測結果 43
3.8.3 模擬結果與實際功率消耗之比較表 46

3.9 討論 47
第四章 總結與相關成果 48
參考文獻 50









圖目錄
第二章 具突波濾波之小面積數位輸出電路
圖2.1：典型數位電路輸出級 7
圖2.2：整體電路架構 9
圖2.3：正向突波濾波器(PSF)電路方塊圖 10
圖2.4：負向突波濾波器(NSF)電路方塊圖 11
圖2.5：熔絲型開關控制式突波濾波器 12
圖2.6：突波產生電路 13
圖2.7：由突波產生器輸入固定週期測試訊號 15
圖2.8：為加上濾波器，針對不同温度，不同供應電壓及不
同模型下之輸出電壓 15
圖2.9：亂數突波產生器輸入測試訊號 16
圖2.10：未加上濾波器電路輸出電壓模擬結果 16
圖2.11：加上濾波器電路輸出電壓模擬結果 16
圖2.12：輸出級電路加上與未加上濾波器之省電效果比較 17
圖2.13：晶片佈局圖 18
圖2.14：測試電路 19
圖2.15：實際量測輸入設定之一 21
圖2.16：實際量測結果之一 22
圖2.17：實際量測輸入設定之二 22
圖2.18：實際量測結果之二 23


第三章 使用高阻抗電路與衝突電路設計之非同步加法器
圖3.1：高阻抗電路 25
圖3.2：衝突邏輯電路 26
圖3.3：一位元全加法器電路的輸出入埠 27
圖3.4：典型的28-T全加法器電路 28
圖3.5：典型的28-T全加法器之進位電路 28
圖3.6：高阻抗邏輯之簡化過程 29
圖3.7：簡化後之進位電路 30
圖3.8：32-T CPL全加法器之 ”和”電路 31
圖3.9：簡化後之“和”電路 32
圖3.10：一位元全加法器之模擬結果 34
圖3.11：八位元全加法器操作在200 MHz頻率之模擬結果
…………………………………………………………35
圖3.12：輸入 Test Vectors : A1~A8 36
圖3.13：輸入 Test Vectors : B1~B8 37
圖3.14：輸出 S1~S8 ，Cout/Cin 38
圖3.15：晶片佈局 40
圖3.16：晶片照相圖 41
圖3.17：一位元全加法器之實測結果 43
圖3.18：輸入 Test Vectors : A1~A8 44
圖3.19：輸入 Test Vectors : B1~B8 44
圖3.20：輸入 Test Vectors : Cin 45
圖3.21：輸出 Test Vectors : S1~S8，COUT.........................……45




表目錄
第二章 具突波濾波之小面積數位輸出電路
表2.1：突波濾波器的預計規格列表 19
表2.2：未加上濾波器功率消耗實測結果 21
表2.3：加上濾波器功率消耗實測結果 21


第三章 使用高阻抗電路與衝突電路設計之非同步加法器
表3.2：28-T，32T與本文所提出之加法器功率延遲積之比
較表 …………………………………………………39
表3.2：本論文所提出之全加法器其他四種不同與本文所提
出之加法器功率延遲積之比較表 …………………..39
表3.3 : 預計規格列表…………………………………………..42
表3.4 : 模擬結果與實際功率消耗之比較表…………………..46

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