Responsive image
博碩士論文 etd-0108110-002334 詳細資訊
Title page for etd-0108110-002334
論文名稱
Title
CoNoC:特殊應用設計之網路晶片全晶片拓樸合成
CoNoC: Fast Full Chip Topology Generation for Application-Specific Network on Chip
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
64
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2009-12-25
繳交日期
Date of Submission
2010-01-08
關鍵字
Keywords
晶片上網路系統拓樸產生、客製化晶片網路
Topology Generation, Custom NoC, Network-on-Chip
統計
Statistics
本論文已被瀏覽 5646 次,被下載 0
The thesis/dissertation has been browsed 5646 times, has been downloaded 0 times.
中文摘要
針對具有特殊需求應用的設計,先前的網路上晶片系統客製化拓樸產生的研究,大部分是進行平面規劃後再增加路由器與連線形成拓樸;而本研究提出於平面規劃時,同時考慮處理器元件與路由器進行平面規劃,而避免針對處理器元件進行平面規劃後,再將路由器增加至處理器元件的平面規劃後,導致的面積估算之不準確性。因將晶片上網路系統(Network-on-Chip, NoC)中的處理器元件與路由器一同進行平面規劃(Co-floorplanning),故稱之為CoNoC。
本研究將客製化晶片上網路系統拓樸產生設計分成兩大部分,一為拓樸產生,二為同時考慮面積與繞線長之平面規劃。拓樸產生部分,選擇適合使用同一路由器之通訊的處理元件,並置於同一路由器的路由器共享群集中,以降低封包跳躍數;再依此拓展成為一個完整的拓樸。
我們所提出的CoNoC 於(1) 平均跳躍數平均減少20.48 % ,(2) 路由器總面積平均減少14.78 % ,(3) 總繞線長度平均減少96.86 % ,(4) 功率消耗平均減少33.20 % ,(5)拓樸產生執行時間平均減少445.45 X。
就MPEG-4 與其放大2X, 4X, 8X, 16X 實驗結果而言,CoNoC 於(1) 平均跳躍數減少1.21 X ,(2) 路由器總面積減少39.30 % ,(3) 總繞線長度減少1.15 X ,(4) 功率消耗減少78.33 % ,(5) 拓樸產生執行時間減少355,089.11 X 。顯示CoNoC 相較於CosiNoc更適用於未來越來越大型的客製化晶片上網路系統設計需求。
Abstract
We propose a synthesis methodology for Network-on-Chips (NoC) or NoC-based multiprocessor systems-on-chip (MPSoCs) for application-specific or irregular topology generation.We first propose simultaneously synthesize both for processor and communication architectures in order to estimate area and routing more accurately during floorplanning stage, which is different with traditional router and link insertion after floorplanning.
Our NoC topology generation is simultaneously optimized for fast, low power and wirelength. Compared with the state of art, our results outperforms averagely 445.45 X in CPU time, 33.20 % in power consumption, and 96.86 % in wirelength at cost of NoC Size of more 2.26 % because our method considering router shape; the number of routers of more 20.63 % because our method only allows router port limit of 5; the number of links of more 3.93 % because our method allows different link lengths.
Also our method is scalable and experiments of 2 X, 4 X, 8 X and 16 X outperform averagely 355,089.11 X in CPU time, 1.21 X in the number hops, 78.33 % in power consumption. Our experimental results show our synthesis method is effective, efficiently and scalable.
目次 Table of Contents
List of Tables............................... iii
List of Figures............................... iv
致謝...........................................vi
Chapter 1 簡介 . . . . . . . . . . . . . . . . . . . . 1
1.1 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 貢獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 論文架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 先前研究 . . . . . . . . . . . . . . . . . . . . 9
Chapter 3 問題描述 . . . . . . . . . . . . . . . . . . . . 12
3.1 輸入. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 輸出. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 定義. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 4 拓樸產生演算法- CoNoC . . . . . . . . . . . . . . . . . . . . 18
4.1 通訊關係分析(Communication Analysis) . . . . . . . . . . . . . . . . . . . 18
4.1.1 獨立有向連線簡化(Independent Arcs Reduction, IAR) . . . . . . . 18
4.1.2 獨立點簡化(Independent Vertex Reduction, IVR) . . . . . . . . . . 20
4.1.3 輸出鄰居子集合樹建構(Outcoming Neighbors Subset Tree Construction,STC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.4 目標端點分解(Target Set Decompose, TSD) . . . . . . . . . . . . . 26
4.2 路由器共享群集集結(RSG Clustering) . . . . . . . . . . . . . . . . . . . . 27
4.2.1 通訊高密度組成(Communication-Intensity-Driven RSG Composition,CIDRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.2 冗餘元素連接(Residual Component Connection, RCC) . . . . . . . 30
4.2.3 路由器共享群集合併(路由器共享群集時Merging, RM) . . . . . . 32
4.2.4 獨立有向連線插入(Independent Arcs Insertion, IAI) . . . . . . . . . 36
4.3 考量晶片面積及繞線長度之平面規劃(Wirelength-Aware Floorplan) . . . . 36
Chapter 5 實驗結果 . . . . . . . . . . . . . . . . . . . . 37
5.1 實驗環境與設定. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2 實驗結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2.1 晶片大小(NoC Size) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.2 跳躍數(Number of Hops) . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.3 路由器個數(Number of Routers) . . . . . . . . . . . . . . . . . . . 39
5.2.4 路由器總面積(Total Router Area) . . . . . . . . . . . . . . . . . . . 39
5.2.5 導線個數(Number of Links) . . . . . . . . . . . . . . . . . . . . . . 40
5.2.6 整體導線長度(Total Wirelength) . . . . . . . . . . . . . . . . . . . 40
5.2.7 功率消耗(Power Consumption) . . . . . . . . . . . . . . . . . . . . 40
5.2.8 執行時間(CPU Time of NoC Topology Generation) . . . . . . . . . 40
5.3 案例研究(Case Study: Scaled MPEG-4) . . . . . . . . . . . . . . . . . . . . 43
5.3.1 晶片大小(NoC Size) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.2 跳躍數(Number of Hops) . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.3 路由器個數(Number of Routers) . . . . . . . . . . . . . . . . . . . 44
5.3.4 路由器總面積(Total Router Area) . . . . . . . . . . . . . . . . . . . 44
5.3.5 導線個數(Number of Links) . . . . . . . . . . . . . . . . . . . . . . 44
5.3.6 整體導線長度(Total Wirelength) . . . . . . . . . . . . . . . . . . . 45
5.3.7 功率消耗(Power Consumption) . . . . . . . . . . . . . . . . . . . . 45
5.3.8 執行時間(CPU Time of NoC Topology Generation) . . . . . . . . . 45
Chapter 6 結論 . . . . . . . . . . . . . . . . . . . . 49
參考文獻 References
[1] H. Zimmermann, “Osi reference model – the iso model of architecture for open systems interconnection,” IEEE Transactions on Communications, vol. 28, pp. 425–432, April 1980.
[2] J. Nurmi, “Network-on-chip:a new paradigm for system-on-chip design,” in Proc. IEEE System-on-Chip, pp. 2–6, Nov. 2005.
[3] W. J. Dally and B. P. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, Jan. 2004.
[4] R. Marculescu, U. Y. Ogras, L.-S. Peh, N. E. Jerger, and Y. Hoskote, “Outstanding research problems in noc design: System, microarchitecture, and circuit perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 3–21, Jan. 2009.
[5] S. Shamshiri and K.-T. Cheng, “Yield and cost analysis of a reliable noc,” in Proc. IEEE VLSI Test Symposium, vol. 00, pp. 173–178, May 2009.
[6] B. S. Feero and P. P. Pande, “Networks-on-chip in a three-dimensional environment: A performance evaluation,” IEEE Transactions on Computers, vol. 58, pp. 32–45, Jan. 2009.
[7] L. P. Carloni, P. Pande, and Y. Xie, “Networks-on-chip in emerging interconnect paradigms: Advantages and challenges,” in Proc. IEEE/ACM Networks-on-Chip,
p. 93V102, May 2009.
[8] S. Murali and G. D. Micheli, “Sunmap:a tool for automatic topology selection and generation for nocs,” in Proc. IEEE/ACM Design Automation Conference, pp. 914–919, June 2004.
[9] M. Dehyadgari, M. Nickray, A. Afzali-kusha, and Z. Navabi, “Evaluation of pseudo adaptive xy routing using an object oriented model for noc,” in Proc. IEEE International Conference on Microelectronics, pp. 204–208, Dec. 2005.
[10] C. J. Glass and L. M. Ni, “The turn model for adaptive routing,” in Proc. IEEE/ACM International Symposium on Computer Architecture, pp. 278–287, April 1992.
[11] G. Ascia, V. Catania, and M. Palesi, “Multi-objective mapping for mesh-based noc architectures,” in Proc. IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp. 182–187, Sept. 2004.
[12] C. Marcon, N. Calazans, F. Moraes, A. Susin, I. Reis, and F. Hessel, “Exploring noc mapping strategies: An energy and timing aware technique,” in Proc. IEEE/ACM Design, Automation, and Test in Europe, vol. 1, pp. 502–507, March 2005.
[13] S. Murali and G. D. Micheli, “Bandwidth-constrained mapping of cores onto noc architectures,” in Proc. IEEE/ACM Design, Automation, and Test in Europe, vol. 2, pp. 896–901, Feb. 2004.
[14] K. Srinivasan and K. S. Chatha, “Layout aware design of mesh based noc architectures,” in Proc. IEEE/ACM international conference on Hardware/Software Codesign and System Synthesis, pp. 136–141, Oct. 2006.
[15] Y. Hu, H. Chen, Y. Zhu, A. A. Chien, and C.-K. Cheng, “Physical synthesis of energyefficient networks-on-chip through topology exploration and wire style optimization,” in Proc. IEEE/ACM International Conference on Computer Design, pp. 111–118, Oct. 2005.
[16] L. Bononi, N. Concer, M. Grammatikakis, M. Coppola, and R. Locatelli, “Noc topologies exploration based on mapping and simulation models,” in Proc. IEEE/ACM Digital System Design Architectures, Methods and Tools, pp. 543–546, Aug. 2007.
[17] F. Pellegrini, PT-Scotch and libScotch 5.1 User’s Guide, Oct. 2008.
[18] S. Murali, L. Benini, and G. D. Micheli, “Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees,” in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, vol. 1, pp. 27–32, Jan. 2005.
[19] C.-L. Chou, U. Y. Ogras, and R. Marculescu, “Energy- and performance-aware incremental mapping for networks on chip with multiple voltage levels,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 1866–1879, Oct. 2008.
[20] S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. D. Micheli, and L. Raffo, “Designing application-specific networks on chips with floorplan information,” in Proc. IEEE/ACM International Conference on Computer Aided Design, pp. 355–362, Nov. 2006.
[21] K. Srinivasan, K. S. Chatha, and G. Konjevod, “Linear-programming-based techniques for synthesis of network-on-chip architectures,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, pp. 407–420, April 2006.
[22] A. Pinto, L. Carloni, and A. Sangiovanni-Vincentelli, “A methodology for constraintdriven synthesis of on-chip communications,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 364–377, March 2009.
[23] K. Srinivasan and K. S. Chatha, “A methodology for layout aware design and optimization of custom network-on-chip architectures,” in Proc. International Symposium on Quality Electronic Design, pp. 352–357, March 2006.
[24] K. Srinivasan, K. S. Chatha, and G. Konjevod, “An automated technique for topology and route generation of application specific on-chip interconnection networks,” in Proc. IEEE/ACM International Conference Computer-Aided Design, pp. 231–237, Nov. 2005.
[25] L. Benini, “Application specific noc design,” in Proc. IEEE/ACM Design, Automation, and Test in Europe, pp. 491–495, March 2006.
[26] A. Jalabert, S. Murali, L. Benini, and G. D. Micheli, “xpipescompiler: A tool for instantiating application-specific networks on chip,” in Proc. IEEE/ACM Design, Automation, and Test in Europe, vol. 2, pp. 884–889, Feb. 2004.
[27] A. Pinto, L. P. Carloni, and A. L. Sangiovanni-Vincentelli, “Efficient synthesis of networks on chip,” in Proc. IEEE/ACM International Conference on Computer Design, pp. 146–150, Oct. 2003.
[28] K. Srinivasan and K. S. Chatha, “Saga: Synthesis technique for guaranteed throughput noc architectures,” in Proc. IEEE/ACM Asia South Pacific Design Automation Conference, vol. 1, pp. 489–494, Jan. 2005.
[29] K. Srinivasan and K. S. Chatha, “Isis: A genetic algorithm based technique for custom on-chip interconnection network synthesis,” in Proc. IEEE/ACM International Conference on VLSI Design, vol. 00, pp. 623–628, Jan. 2005.
[30] S. Yan and B. Lin, “Application-specific network-on-chip architecture synthesis based on set partitions and steiner trees,” in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 277–282, March 2008.
[31] J. Chan and S. Parameswaran, “Nocout : Noc topology generation with mixed packetswitched and point-to-point networks,” in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 265–270, Jan. 2008.
[32] B. S. Feero and P. P. Pande, “Min-cut floorplacement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, pp. 1313–1326, July 2006.
[33] S. Yan and B. Lin, “Custom networks-on-chip architectures with multicast routing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, pp. 342–355, March 2009.
[34] T.-C. Chen, Y.-W. Chang, and S.-C. Lin, “A new multilevel framework for large-scale interconnect-driven floorplanning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 286–294, Feb. 2008.
[35] A. B. Kahng, B. Li, L.-S. Peh, and K. Samadi, “Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration,” in Proc. IEEE Design, Automation and Test in Europe, pp. 423–428, April 2009.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內校外均不公開 not available
開放時間 Available:
校內 Campus:永不公開 not available
校外 Off-campus:永不公開 not available

您的 IP(校外) 位址是 54.166.223.204
論文開放下載的時間是 校外不公開

Your IP address is 54.166.223.204
This thesis will be available to you on Indicate off-campus access is not available.

紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code