多媒體應用在嵌入式系統中一直扮演著很重要的角色，產品更是五花八門，諸如各種酷炫造型的手機、輕巧而方便攜帶的MP3 player及上班族的最愛PDA等都是我們日常生活中無時無刻在接觸的。因此這類的產品通常都不會是高價位的，而誰的設計與生產成本低誰就能在這競爭的市場上獲利。所以在眾多的多媒體應用中，最流行的MP3應用就為我們選擇研究的目標。
目前有關MP3 player的設計方法不外乎是利用高效能的處理器或是利用通用處理器(general purpose processor)搭配一顆運算能力很強的數位訊號處理器(DSP)來達成。其效能雖能滿足多媒體運算的要求，但是同時也在系統中增加了不少硬體成本，這在許多強調低成本更甚於高效能的嵌入式產品當中，這或許不是最佳的解決方案。
因此，在本篇論文的焦點將會放在MP3軟體演算法的最佳化上，透過對MP3解碼演算法的分析，找出其中的關鍵運算，利用本實驗室自行發展的低成本多媒體微控器(命名為ME-MCU)的SIMD運算特性予以加速，使得我們不需要用一顆運算能力很強的CPU或DSP而同樣也能完成MP3的解碼動作。我們也希望對軟體演算法做最佳化的同時，也能對ME-MCU之後續改良能提供一些建議，以期能使之更加適合於多媒體的應用。

Multimedia workloads have always held an important role in embedded applications. Products are multifarious, such as various modeling mobile phone, MP3 player which is deft and convenient to carry and PDA which is popular with workers. We touch them all the time in our life. So these kinds of products are usually not high price. If their design cost and production cost are lower than others, then they can earn profits in this competition market. In so much multimedia applications, the most popular MP3 is our research goal.
The design methods of multimedia audio application are using high performance CPU or combining general purpose processor with a DSP. Their performance satisfied the demand of multimedia application really, but the system hardware cost will increase at the same time. It is not the best solution in embedded products which emphasizing that low cost is better than high performance.
So, my thesis will focus on MP3 algorithm optimization. We analyzed MP3 decoder algorithms, and found out the key operation. Using the SIMD operation feature of low cost multimedia processor development from our lab (It’s named ME-MCU) to accelerate the processor speed. Then, I don’t need a strong CPU or DSP, and I also can complete the MP3 decode operations as well. When I optimized the MP3 algorithm, I hope to provide some suggestion for ME-MCU modification. And the multimedia application will more agree with ME-MCU.

Chapter 1. Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Proposed Method 3
1.4 Contribution 4
1.5 Thesis Organization 4
Chapter 2. Related Work 5
2.1 Software optimization techniques for embedded systems 5
2.2 Hardware design techniques for embedded systems 7
Chapter 3. Platform Architecture 12
3.1 Multimedia Instruction Set Extension 12
3.1.1 Single Instruction Multiple Data, SIMD 12
3.1.2 Multimedia Operations 13
3.2 MCU Architecture 16
3.2.1 CPU 17
3.2.2 Interface to Data Memory 19
3.2.3 Peripheral modules 20
Chapter 4. Principle and analysis of MP3 Decoding Algorithm 22
4.1 MP3 Introduction 22
4.2 MP3 Frame format 24
4.2.1 Header format 24
4.2.2 Side information 27
4.2.3 Main (Audio) Data and Ancillary Data 29
4.3 MP3 Decoding flow 29
4.3.1 Synchronization、Header decoding and Side information decoding 30
4.3.2 Scale factor decoding 30
4.3.3 Huffman decoding 31
4.3.4 De-quantization 31
4.3.5 Stereo processing 32
4.3.6 Reorder processing (使用短窗框時才須要執行) 33
4.3.7 Alais processing (使用長窗框時才須要執行) 34
4.3.8 IMDCT processing 35
4.3.9 Polyphase Synthesis processing 37
Chapter 5. Optimization for Performance/Cost 39
5.1 MP3 algorithm optimization (C level) 39
5.2 Fixed-point 41
5.3 Memory layout 45
5.4 Register Allocation 47
5.5 MME/DSP feature optimization 48
5.5.1 Huffman decoder optimization 49
5.5.2 Dequqntization optimization 51
5.5.3 Stereo optimization (only short window) 53
5.5.4 Alias reduction optimization (only long window) 56
5.5.5 IMDCT optimization 58
5.5.6 Poly-phase synthesis optimization 60
Chapter 6. Hardware Feature Tradeoffs 64
6.1 MME instruction set 64
6.2 Data size 66
6.3 Memory size 67
6.3.1 Program Memory，PM 68
6.3.2 Read Only Memory，ROM 69
6.3.2 Data Memory，DM 71
Chapter 7 Verification 72
7.1 MP3 C program 72
7.2 MP3 assembly code 75
Chapter 8. Experiments 78
8.1 Instruction counts/Clock cycle counts/Power/Chip size 78
8.2 MME instruction contribution 82
Chapter 9. Conclusion 84
參考文獻(References) 87
附錄A (Appendix A) – ME-MCU指令編碼表 89
附錄B (Appendix B) – Memory Mapped Registers 94
附錄C (Appendix C) – Side information 97
附錄D (Appendix D) – Poly-phase synthesis assembly code 100
附錄E (Appendix E) – Dynamic instructions (short window) 101
附錄F (Appendix F) – DSP56654 Chip Features 104

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