近年來，生物醫學電子工程和行動裝置的緊密結合，無論是新興的人體穿戴裝置、甚至是人工智慧的發展，神經生醫工程已成為熱門的科學及領域。本論文提出應用於測試生物醫學訊號之傳遞的神經仿真器，其功用在於降低活體實驗的需求，並提供穩定且可重複之使用性。此仿真器可以模擬自然的神經傳遞行為，並提供人工神經介面給待測電路做測試，它在阻抗、電極、電壓以及動作電位傳遞特色上足以代表一個真實的神經。
此人工神經仿真器採用二進位電荷重新分佈式與循環式之十位元數位類比轉換器，資料通訊協定則是使用序列周邊介面，在輸出級部分適用於產生跨膜動作準位訊號(transmembrane action potentail) ±200mV之生醫訊號。
。此晶片使用於三百五十奈米金氧半場效電晶體。在單一電壓源三伏下，功率消耗為1.38mW，晶片有效面積為0.157毫米平方。量測結果顯示最大微分非線性誤差(Differential Nonlinearity, DNL) 為±2.1 LSB，最大積分非線性誤差(Integral Nonlinearity, INL) 為±2.2 LSB。

This thesis realizes an application-specific integrated circuit (ASIC) implementation of 10-bit digital-to-analog converter (DAC) and a Truly Floating Voltage Source output stage in CMOS technology. The circuit is intended to be used as a core building block of an artificial nerve fiber (nerve emulator). The circuit receives the digital input signal, which in the target application is an emulation of the nerve transmembrane action potential (TMAP), and provides the voltage signal in the amplitude range of about ±200 mV at its differential voltage output nodes. The DAC uses binary scaled capacitors to generate the 8 least significant bits and it is followed by a cyclic converter stage to add the two most significant bits. This combination yields a suitable trade-off between converter speed, area and power consumption. A serial peripheral interface (SPI) is implemented to receive the input code sequentially to minimize the number of chip pins. Measured results of the ASIC fabricated in 0.35 µm CMOS technology are presented which show integral non-linearity (INL) below ±2.2 LSB and differential non-linearity (DNL) below ±2.1 LSB, a circuit active area of 0.157 mm2 and a power consumption of 1.38 mW when operated from a 3 V supply.

誌謝............................................................................i
摘要............................................................................ii
Abstract......................................................................iii
Contents.....................................................................v
List of Figures.............................................................vii
List of Tables...............................................................x
Chapter 1 Introduction.................................................1
1.1 Background...........................................................1
1.2 Motivation for floating DAC.....................................2
1.3 Contributions and organization of thesis...................6
Chapter 2 Circuit Design.............................................8
2.1 Digital-to-analog conversion....................................8
2.1.1 Static Performance Specification of Converters.....9
2.1.2 DAC Architectures..............................................12
Chapter 3 DAC implementation...................................18
3.1. Charge-scaling sub-DAC implementation................19
3.1.1 Switch...............................................................20
3.1.2 Output buffer......................................................21
3.1.3 Quasi-passive cyclic sub-DAC............................22
3.1.4 Serial to parallel interface...................................25
3.1.5 Floating voltage source output stage...................29
3.2 Chip layout.............................................. ...........34
Chapter 4 Measured Result.......................................35
4.1 ASIC in D35 technology.......................................35
4.2 Measurement Setup............................................36
4.3 ASIC Measurement.............................................38
4.3.1 Measurement of 8-bit sub-DAC..........................38
4.3.2 Measurement of cyclic sub-DAC.......................40
4.3.3 Measurement of 10-bit DAC..............................42
4.3.4 Measurement of buffer.....................................43
4.3.5 Measurement of SPI module............................45
4.3.6 Measurement of floating voltage output.............46
4.4 AP generation...................................................49
4.5 Comparison......................................................50
Chapter 5 Conclusions and future work................. ..52
5.1 Conclusions................................................... .52
5.2 Future work......................................................53
References...........................................................54

[1] J. Gunther, “Impulse conduction in the myelinated giant fibers of the earthworm. Structure and function of the dorsal nodes in the median giant fiber.” Journal of Comparative Neurology, 168, 505-532
[2] R. Rieger, M. Schuettler, and S.C. Chuang, “A Device for Emulating Cuff Recordings of Action Potentials Propagating Along Peripheral Nerves.” IEEE Trans. On Neural systems and rehabilitation Eng., vol.22, no. 5, SEPTEMBER 2014.
[3] G. A. M. Kurstjens, “Nerve conduction velocity selective recording using a multi-contact cuff electrode-A case study of in vitro vagus nerve preparation,” in Proc. 15the IEEE Nordic-Baltic Conf. Biomedical Engineering Medical Physics, 2011, pp.261-263.
[4] N. Donalson, R. Rieger, M. Schuettler, and J. Taylor, “Noise and Selectiveity of Velocity-Selective Multi-Electrode Nerve cuffs.” Medical & Biological Engineering & Computing, pp.634-643, 2008.
[5] J. Taylor and R. Rieger, “A Low Noise Front-end for Multiplexed ENG Recording using CMOS Technology,” Analog Integrated Circuits & Signal Processing, vol. 68, no. 2, pp. 163-174, 2011.
[6] Elaine N. Marieb, P. B. Wilhelm and Jon B. Mallatt, “Human Anatomy: Pearson New International Edition.” 7th edition, uk, England, pp. 293-506, 2014.
[7] Action potential in Encyclopadia Britannica [online]
Available: https://global.britannica.com/science/action-potential
[8] J. J. Struijk, “On the spectrum of nerve cuff electrode recordings,” in Proc. 19th Ann. Int. Conf. EMBS, 1997, vol. 5, pp. 2006-2007.
[9] X. Shaojun, K.C. McGill, V.R. Hentz, “Experimental verification of nerve conduction linearity,” in Proc. 18th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, vol.4, pp. 1775-1776,1996.
[10] P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design”, 2nd edition, Oxford, 2002
[11] R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation”, 3rd edition, John Wiley & sons Inc., 2010.
[12] B. Razavi, “Fundamentals of Microelectronics,” 1st edition, John Wiley & sons Inc., 2008
[13] R. E. Suarel, P. R. Gray, and D. Hodges, “All-MOS charge redistribution analog-to-digital conversion techniques-Part II,” IEEE J. Solid-State Circuits, vol. SSC-10, no. 6, pp. 379-385, Dec. 1975.
[14] L. Weyten and S. Audenaert, “Two-capacitor DAC with compensative switching,” Electron. Lett., vol.31, pp. 1435-1436, Aug. 1975.
[15] P. Rombouts and L. Weyten, “Linearity improvement for the switched capacitor DAC,” Electron. Lett., vol.32, pp. 293-294, Feb. 1996.
[16] D. Johnson, “Implementing serial bus interfaces using general purpose digital instrumentation,” IEEE Instrumentation Measurement Magazine, vol. 13, no. 4, pp. 8-13, August 2010.
[17] SPI Block Guide v. 03.06, Motorola Semiconductor Products Inc. Std. S12SPIV3/D
[18] Texas Instruments Inc., LM134/:M324/LM334 3-Terminal Adjustable Current Sources datasheet rev. C, Dallas, TX, 2004.
[19] Microchip Technology Inc., “PIC18F2420/2520/4420/4520 Data sheet: 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nano Watt Technology datasheet DS39631E, Chandler, AZ, 2008.
[20] “PICkit 3 Programmer/Debugger User Guide,” Microchip Technology Inc., Chandler, AZ.
[21] National Instruments Inc., NI USB-6211 data sheet, Austin TX.
[22] W. Ni, X. Geng, Y. Shi, and F. Dai, “A 12-bit 300 Mhz CMOS DAC for High-speed System Applications”, IEEE International Symposium on Circuits and Systems, Sept. 2006, pp. 1402-1405.
[23] B. Ma, Q. Huang and F. Yu, “A 12-bit 1.74-mW 20-MS/s DAC with Resistor-String and Current-Steering Hybrid Architecture,” IEEE System-on-chip Conference (SOCC), 2015 28th.
[24] C. W. Lu and L. C. Huang, “A 10-bit LCD column driver with piecewise linear digital-to-analog converters,” IEEE J. Solid-State Circuits, vol.43, no. 2, pp. 371-378, Feb 2008.
[25] P. J. Liu and Y. J. Chen, “A 10-bit CMOS DAC With Current Interpolated Gamma Correction for LCD Source Drivers,” IEEE Transactions on circuits and systems for video technology, vol. 22, no. 6, Jun 2012