影像解碼器在電視接收機，尤其是NTSC (美國國家電視標準委員會) 電視中，扮演非常重要的角色。本文以雙線延遲梳形濾波器設計實作NTSC電視系統之影像解碼器，並設計梳形濾波器內儲存掃描線資料之低功率靜態記憶體以及傳輸數位資料之低功率小面積輸入/輸出單元。
提出的影像解碼器中，數位鎖相迴路使用四倍角公式無唯讀記憶體的直接數位頻率合成數位控制振盪器解決相位鎖定的問題。色度解調器內部的兩個低通濾波器則使用20階移位式有限區間脈衝響應濾波器，並且截取係數中不必要的小數，以降低成本。
靜態記憶體使用負字線電壓控制記憶體單元的存取電晶體，以降低記憶體單元的待機漏電流。另外，亦採用分割記憶庫、脈波閘控等方式，更進一步降低記憶體的功率消耗。
輸入/輸出單元提出一個與目前常用的輸出入單元完全不同的概念，採用降低輸出信號振幅和多臨界電壓電晶體方式，使整個晶片的成本及功率消耗均大幅的降低。

Video decoders play a very important role in the TV receivers. This is especially true for NTSC-based TVs. The design and implementation of the video decoder with two-line delay comb filter are presented. Moreover, the works includes the low-power SRAM (static random access memory) in the comb filter for storing scanning line data and the low-power small-area I/O cells for transmitting digital data.
A digital phase lock loop (PLL) in the proposed video decoder uses a ROM-less 4θ-based direct digital frequency synthesizer (DDFS)-based digital control oscillator to resolve the false locking problem. Two 20-tap transposed FIRs (finite-duration impulse response filter) are used to implement the low pass filters (LPF) in the chrominance demodulator. Besides, the unnecessary decimals of the coefficients of the LPF are truncated to reduce hardware cost.
The proposed SRAM takes advantage of a negative word-line voltage controlling the access transistors of the memory cell to reduce the leakage current in the standby mode. Besides, a memory bank partition scheme and a clock gating scheme are also used to save more power.
Finally, a fully different concept from current I/O designs is proposed. The novel I/O cell takes advantage of reducing output voltage swing as well as transistors with different threshold voltages such that the area and power consumption of overall chip can be drastically reduced.

1. Introduction 1
1.1 Motivation 1
1.2 Related Prior Works 3
1.2.1 Video decoder 3
1.2.2 Low power SRAMs 5
1.2.3 Digital I/O cell 7
1.3 Organization of this Dissertation 8
2. Low-cost Video Decoder with 2D2L Comb Filter for NTSC TVs 9
2.1 Digital Video Decoder Design 9
2.1.1 Comb filter 10
2.1.2 Clock recovery by DDFS-based DCO 11
2.1.2.1 Digital PLL 11
2.1.2.2 ROM-less DDFS 15
2.1.2.3 Synchronization circuitry for color burst and sub-carrier signals 16
2.1.2.4 Chrominance Demodulator 17
2.2 Simulation and Implementation 19
2.3 Summary 20
3. 4-kb Negative Word-line Gate Drive Low-power SRAM 22
3.1 Low Power 4-T SRAM Design 22
3.1.1 Leakage current comparison of the NB and the NWL schemes 23
3.1.2 Leakage current comparison of NMOS and PMOS FETs 24
3.1.3 Power consumption comparison of two types of loadless CMOS 4-T SRAM cell 25
3.2 Simulation and Implementation 32
3.2.1 Simulation 32
3.2.2 Implementation and measurement 36
3.3 Summary 40
4. Low-power Small-area Digital I/O cell 44
4.1 Low-Power I/O C3ll Design 44
4.1.1 Transmitter of the proposed I/O cell 45
4.1.2 Receiver of the proposed I/O cell 47
4.2 Simulation and Physical Measurements 49
4.2.1 Simulation 49
4.2.2 Physical measurements 50
4.3 Summary 51
5. Conclusion and Future Works 55
5.1 Conclusion 55
5.2 Future Works 56
Bibliography 56

[1] W. Chung, T. J. Endres, and C. D. Long, “A data broadcasting system expanding the information capacity of existing analog communication systems,” IEEE Trans. on Broadcasting, vol. 51, no. 2, pp. 180-190, June 2005.
[2] B. Sheng, W. Gao, D. Xie, and D. Wu, “An Efficient VLSI architecture of VLD for AVS HDTV decoder,” IEEE Trans. on Consumer Electronics, vol. 52, no. 2, pp. 696-701, May 2006.
[3] H. Jia, P. Zhang, D. Xie, and W. Gao, “An AVS HDTV video decoder architecture employing efficient HW/SW partitioning,” IEEE Trans. on Consumer Electronics, vol. 52, no. 4, pp. 1447-1453, Nov. 2006.
[4] S. Wen, “Representations of relative display gamut size,” IEEE/OSA J. of Display Technology, accepted for future publication, 2007.
[5] ETSI, “Data services, framing structure, channel coding and modulation for digital terrestrial television,” Ref prETS 300 744, Mar. 1996.
[6] Y. C. Faroudja, “NTSC and beyond,” IEEE Trans. on Consumer Electronics, vol. 34, no. 1, pp. 166-178, Feb. 1988.
[7] M. Ohta, K. Kohiyama, N. Tahara, K. Sugihara, F. Asami, O. Kobayashi, Y. Hino, and T. Akiba, “A single-chip CMOS analog/digital mixed NTSC decoder,” IEEE J. of Solid-State Circuits, vol. 25, no. 6, pp. 1464-1469, Dec. 1990.
[8] C.-C. Wang, Y.-L. Tseng, C.-C. Chen, and C.-S. Chen, “Low-cost NTSC digital video decoder using 4θ-based DDFS,” in Proc. Workshop on Consumer Electronics (WCE2003), pp. 41 (CD-ROM version), Nov. 2003.
[9] K. Jack, “Video demystified,” 3rd ed., Eagle Rock, VA: LLH Technology Publishing, 2001.
[10] B. Gorb and C. Herndon, “Basic television and video systems,” 6th ed., New York: Glencoe/McGraw-Hill, 1998.
[11] J.-S. Wu, M.-L. Liou, H.-P. Ma, and T.-D. Chiueh, “A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrum transceiver IC,” IEEE J. of Solid-State Circuits, vol. 32, no. 10, pp. 1499-1510, Oct. 1997.
[12] C. Scarpa, “A recursive NTSC canceler to reduce co-channel interference into HDTV broadcasts,” IEEE Trans. on Consumer Electronics, vol. 39, no. 3, pp. 696-703, Aug. 1993.
[13] Texas Instruments, “Function of a video decoder-NTSC, PAL and SECAM digital decoding,” Training Menu: TI040226M, Feb. 2004.
[14] I. E. G. Richardson, “Video codec design,” New York: Wiley, 2002.
[15] C.-C. Kuo and Y.-T. Chen, “New method for the implementation of an NTSC digital video decoder,” IEEE Trans. on Consumer Electronics, vol. 48, no. 2, pp. 265-274, May 2002.
[16] V. Pasham, A. Miller, and K. Chapman, Application Note: “Transposed form FIR filter,” Xilinx Inc., Oct. 2001. [Online]. Available: http://www.xilinx.com/bvdocs/ appnotes/xapp219.pdf.
[17] Philips, “PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler,” Data Sheet: SAA7114H, Mar. 15, 2000.
[18] Philips, “A single-chip multimedia engine,” Data Sheet: TriMedia TM-1100, 1998.
[19] Philips, “Multistandard vision and sound-IF PLL with DVB-IF processing,” Data Sheet: TDA9819, July 14, 1998.
[20] Micronas, “Digital receiver front-end,” Data Sheet: DRX 3960A, Oct. 2000.
[21] Broadcom, “HDTV/CATV receiver,” Data Sheet: BCM 3510, 2001.
[22] Trchwell, “Enhanced video decoder with component inputs,” Data Sheet: TW99, Sep. 28, 2000.
[23] United States Patent, “Technique to stabilize the chrominance subcarrier generation in a line-locked digital video system, Patent no. 6741289, May. 2004.
[24] United States Patent, “Phase comparison and phase adjustment for synchronization to a reference signal that is asynchronous with respect to a digital sampling clock,” Patent no. 6310653, Oct. 2001.
[25] United States Patent, “Digital color signal reproducing circuit,” Patent no. 6538702, Mar. 2003.
[26] United States Patent, “Clock generator for digital video signal processing apparatus,” Patent no. 6034735 Mar. 2000.
[27] B. Prince, “Semiconductor memories,” New York: Wiley, 1991.
[28] S.-M. Yoo, J. M. Han, E. Hag, S. S. Yoon, S.-J. Jeong, B. C. Kim, J.-H. Lee, T.-S. Jang, C. J. Park, D. H. Seo, C. S. Choi, S.-I. Cho, and C. G. Hwang, “A 256M DRAM with simplified register control for low power self refresh and rapid burn-in,” in Proc. Symp. VLSI Circuits Dig. Tech. Papers, pp. 85-86, Oct. 1994.
[29] K. Itoh, K. Sasaki, and Y. Nakagome, “Trends in low-power RAM circuit technologies,” in Proc. of the IEEE, vol. 83, no. 4, pp. 524-534, Apr. 1995.
[30] K. Itoh, S. Kimura, and T. Sakata, “VLSI memory technology: current status and future trend,” in Proc. 25th European Solid-State Conference (ESSCIRC'99), pp. 3-10, Sept. 1999.
[31] K. Takeda, Y. Aimoto, N. Nakamura, H. Toyoshima, T. Iwasaki, K. Noda, K. Matsui, S. Itoh, S. Masuoka, T. Horiushi, A. Nakagawa, K. Shimogawa, and H. Takahashi, “A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro,” IEEE J. of Solid-State Circuits, vol. 35, no. 11, pp. 1631-1640, Nov. 2000.
[32] K. Itoh, “VLSI memory chip design,” Heidelberg: Springer, 2001.
[33] H. Kawaguchi, Y. Itaka, and T. Sakurai, “Dynamic leakage cut-off scheme for low-voltage SRAM's,” in Proc. Symp. on VLSI ircuits, pp. 140-141, June 1998.
[34] C.-C. Wang, P.-M. Lee, and K.-L. Chen, “An SRAM design using dual threshold voltage transistors and low-power quenchers,” IEEE J. of Solid-State Circuits, vol. 38, no. 10, pp. 1712-1720, Oct. 2003.
[35] C.-C. Wang, Y.-L. Tseng, H.-Y. Leo, and R. Hu, “A 4-Kb 500-MHz 4-T CMOS SRAM using low-Vthn bitline drivers and high-Vthp latches,” IEEE Trans. VLSI System, vol. 12, no. 9, pp. 901-909, Sep. 2004.
[36] T. Yamagata, S. Tosishima, M. Tsukude, T. Tsuruda, Y. Hashizume, and K. Arimoto, “Low voltage circuit design techniques for battery-operated and/or giga-scale DRAM's,” IEEE J. of Solid-State Circuits, vol. 30, no. 11, pp. 1183-1188, Nov. 1995.
[37] S. Eto, M. Matsumiya, M. Takita, Y. Ishii, T. Nakamura, K. Kawabata, H. Kano, A. Kitamoto, T. Ikeda, T. Koga, M. Higashiho, Y. Serizawa, K. Itabahi, O. Tsuboi, Y. Yokoyama, and K. Kimura, “A 1-Gb SDRAM with ground-level precharged bit line and non-boosted 2.1-V word line,” IEEE J. of Solid-State Circuits, vol. 33, no. 11, pp. 1697-1702, Nov. 1998.
[38] H. Tanaka, M. Aoki, T. Sakata, S. Kimura, N. Sakashita, H. Hidaka, T. Tachibana, and K. Kimura, “A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme,” IEEE J. of Solid-State Circuits, vol. 34, no. 8, pp. 1084-1090, Aug. 1999.
[39] R. J. Baker, H. W. Li, and D. E. Boyce, “CMOS - circuit design, layout, and simulation,” New York: Wiley, 1998.
[40] C.-C. Wang, T.-H. Chen and R. Hu, “A 4-Kb 667-MHz CMOS SRAM using dynamic threshold voltage wordline transistors,” in Proc. Southwest Symp. Mixed-Signal Design, pp. 90-93, Feb. 2003.
[41] M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano, and T. Nakano, “A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM,” IEEE J. Solid-State Circuits, vol. 18, no. 5, pp. 479-485, Oct. 1983.
[42] D.-H. Wang, Q. Jing, Y.-G. Li, and C.-H. Hou, “Low power design in 100 MHz embedded SRAM,” in Proc. 4th International Conference on ASIC, pp. 599-602, Oct. 2001.
[43] T. Hirose, H. Kuriyama, S. Murakami, K. Yuzuriha, T. Mukai, K. Tsutsumi, Y. Nishimura, Y. Kohno, and K. Anami, “A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture,” IEEE J. Solid-State Circuits, vol. 25, no. 5, pp. 1068-1074, Oct. 1990.
[44] A. Roberts, J. Dreibelbis, G. Gabric, L. Gilbert, R. Goodwin, E. Hedberg, T. Maffitt, L. Meuniar, D. Moran, N.-Y. Phuong, D. Reed, D. Reismiller, and R. Sasaki, “A 256K SRAM with on-chip power supply conversion,” in Proc. IEEE International Solid-State Circuits Conference, pp. 252-253, Feb. 1987.
[45] K. Noda, K. Matsui, K. Takeda, and N. Nakamura, “A loadless CMOS four-transistor SRAM cell in a 0.18-um logic technology,” IEEE Transactions on Electron Devices, vol. 48, no. 12, pp. 2851-2856, Dec. 2001.
[46] O. Minato, T. Masuhara, T. Sasaki, K. Matsumoto, Y. Sakai, and T. Hayashida, “A 20 ns 64K CMOS static RAM,” IEEE J. of Solid-State Circuits, vol. 19, no. 6, pp. 1008-1013, Dec. 1984.
[47] C.-C. Wang, Y.-L. Tseng, C.-C. Li, and R. Hu, “A 1.26 ns access time current-mode sense amplifier design for embedded SRAMs,” in Proc. 14th VLSI Design/CAD Symp., vol. C3-6, pp. 377-380, Aug. 2003.
[48] S. Hattori, and T. Sakurai, “90% write power saving SRAM using sense-amplifier memory cell,” in Proc. Symp. on VLSI Circuits, pp. 46-47, June 2002.
[49] P. K. Lala, and A. Walker, “An on-chip test scheme for SRAMs,” in Proc. International Workshop on Memory Technology, Design and Testing, pp. 16-20, Aug. 1994.
[50] http://www.labs.nec.co.jp/Eng/Topics/data/r000131/
[51] A. Boni, A. Pierazzi, and D. Vecchi, “LVDS I/O interface for Gb/s-per-pin operation in 0.35-um CMOS,” IEEE J. of Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr. 2001.
[52] M.-D. Ker, and C.-H. Chuang, “Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface,” IEEE Electron Device Letters, vol. 23, no. 6, pp. 363-365, June 2002.
[53] M.-D. Ker, and C.-H. Chuang, “Electrostatic discharge protection design for mixed-voltage CMOS I/O Buffers,” IEEE J. of Solid-State Circuits, vol. 37, no. 8, pp. 1046-1055, Aug. 2002.
[54] M. M. Lee, “Secondary protection scheme for CMOS I/O buffers and core circuits and their ESD sensitivity,” in Proc. 6th Inter. Physical & Failure Analysis of Integrated Circuits Symp., pp. 109 - 114, 1997.
[55] Philips Semiconductor Inc., “IBIS model of 74AHCT04,” Version 1.3, Dec. 15, 2000.
[56] F. Wajsburt, K. Dioury, and F. Petrot, “Low power, process independent, full transistor controlled slew rate, PCI compliant I/O pads,” in Proc. 21st International Conference on Microelectronics, vol. 2, pp. 811-814, Sep. 1997.
[57] Data sheet: “TSMC 0.25um mixed-signal 2P5M PIP or 1P5M+ MIM salicide 2.5 V/5.0 V or 2.5 V/3.3 V design guideline,” 2000.
[58] B. Razavi, “Design of analog CMOS integrated circuits,” New York: McGraw Hill, 2002.