在這篇論文中，我們研究低溫複晶矽薄膜電晶體（LTPS TFTs）在經過電性交流偏壓後的劣化特性與機制。從實驗結果顯示出N型電晶體與P型電晶體在不同交流偏壓頻率的操作之下，所造成的劣化特性與機制是不同的。
在P型複晶矽薄膜電晶體中，我們觀察到臨限電壓在經由電性交流偏壓後造成的劣化是與測試頻率有緊要的關係。在低頻操作時，臨限電壓造成的劣化是比在高頻時還要嚴重的。元件在經過電性測試後的劣化主要來自於元件本身的自我加熱(Self-heating)而加速了負偏壓溫度之不穩定性(Negative Bias Temperature Instability)。而且，當環境溫度越來越大時，元件劣化（如臨限電壓偏移的程度與S.S 劣化）的速度會被加速。因此，我們認為臨限電壓的劣化機制是由晶界(Grain Boundary)和絕緣層與多晶矽的界面(Interface)的Si-H鍵產生斷鍵而造成的。
在N型複晶矽薄膜電晶體中，不同的交流偏壓頻率之下所造成的劣化特性歸因於溫度效應以及熱載子效應。在低頻操作之下，臨限電壓向右劣化以及遷移率會提高的現象首先在100秒的電性測試後被發現到。我們認為此時的溫度效應帶來的影響大於缺陷的產生效應帶來的影響。然而，臨限電壓反方向向左移動以及遷移率會降低的現象在500秒的電性測試後被發現。我們認為此時缺陷的產生帶來的影響大於溫度效應帶來的影響。在高頻操作之下，由於電晶體開關次數多使得在汲極端產生缺陷的效應使得電流以及遷移率皆下降。

In this research, the degradation effect of the low temperature polycrystalline silicon TFTs (LTPS TFTs) under dynamic stress was investigated. The experiment results revealed that the degenerate behaviors of n- and p-type poly-Si were different.
In p-channel TFT, it was observed that the degradation of threshold-voltage (Vth) was closely associated with the stress frequency of ac stress. The degradation was more serious at low-frequency stress than that at high-frequency stress. The degradation of electrical characteristics of device is mainly dominated by the self-heating enhanced negative bias temperature instability effect. Moreover, the increased temperature around the environment could make the degradation of characteristics more serious, such as Vth shift (fixed charge), degraded S.S (dangling bonds). We suggest that the generation of deep states originated from bond broken at both of grain-boundary and interface state was explained the degradation mechanism of threshold-voltage.
In n-channel TFT, the degradation characteristics may be attributed to both of the temperature effect and the hot carrier effect under the different stress frequency. At low-frequency stress, Vth shift (positively) and mobility are increased after 100 seconds stress because of the temperature effect. However, Vth shift (negatively) and mobility are decreased after 500 seconds stress because of the effect of the state creation near the drain regime. At high-frequency stress, the times of the switch is numerous, and result in the on-state current decreased because of the trap state generated.

Contents
Chinese Abstract i
English Abstract iii
Acknowledgement v
Contents vii
Figure Captions ix
Chapter 1.Introduction 1
1-1. Introduction of the Polycrystalline Silicon Thin-Film Transistor 1
1-2. Introduction of Defects in poly-Si TFTs 4
1-3. Introduction of Negative Bias Temperature Instability 5
1-4. Introduction of Seto’s model 9
1-5. Motivation and Organization of This Thesis 13
Reference 15
Chapter 2.Fabrication and characterization 21
2-1. Device Fabrication 21
2-1-1.Technology of ELA Crystallization 21
2-1-2.Fabrication Processes of LTPS Poly-Si Device 22
2-2. Basic characterization of the LTPS TFT 23
2-2-1.The I-V transfer characteristics in poly-Si TFT 23
2-2-2.The C-V transfer characteristics in poly-Si TFT 25
Reference 27
Chapter 3.Instruments and parameter extraction 28
3-1. Instruments and measurement setup 28
3-1-1.Instruments 28
3-1-2.Set up instruments for I-V and C-V 29
3-2. Methods of Device Parameter Extraction 29
3-2-1. Determination of the threshold voltage 29
3-2-2. Determination of the field-effect mobility 31
3-2-3. Determination of on/off current ratio 31
3-2-4. Determination of the subthreshold swing 32
3-2-5. Determination of the trap density 32
Reference 35
Chapter 4.Results and Discussion 36
4-1. The Degradation of P-channel TFT under pulse 36
4-1-1.The pulse effects 36
4-1-2.The temperature effects 37
4-1-3.Capacitance measurement with variable frequency 39
---determination of the degradation mechanism and regions.
4-2. The Degradation of N-channel TFT under pulse 42
4-2-1. Introduction of the degradation characteristics 42
4-2-2. The effects of low-frequency ac stress 43
4-2-3. The effects of high-frequency ac stress 46
Reference 47
Chapter 5. Conclusion 50
Figures 52

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