在本論文中，具有雙源極、雙汲極的十字型閘極SOI MOSFET已經被成功的製作出來了。此一新SOI元件的結構具有下列五項特點：
（1） 以平台式隔離代替傳統LOCOS隔離及溝渠式隔離兩種方式：這樣的隔離方式不但可避免鳥嘴效應，同時也免除了在矽晶膜中挖溝渠的複雜度跟困難度，簡化了隔離製程。
（2） 以三面閘極結構代替傳統單面閘極結構：MOS元件的汲極電流大小和元件的通道寬度成正比，所以在新元件的結構中，除了矽晶膜層上方的多晶矽閘極之外，我們更在矽晶膜層的垂直方向厚度形成了另外兩面閘極，以達到能不降低電路集積密度而增加元件的有效寬度，提高元件的電流驅動力。
（3） 以四條通道結構代替傳統單一通道結構：MOS元件的汲極電流大小跟通道數目成正比，所以我們以增加通道數目的方式提高元件的電流驅動力。
（4） 縮小源極跟汲極的區域減少漏電流：當MOS元件擁有多條通道之時，漏電流也會因此增加，所以我們縮小源極跟汲極區域，藉此減少漏電流值。
（5） 有著雙源極跟雙汲極：單一源極跟汲極的傳統MOS元件必須用到較多的元件才能控制雙倍或是減半的電流量，而雙源極跟雙汲極的元件只需要一個元件就能達到。在電路設計上，只要運用3D立體製程整合的技術，便可以將源極跟汲極的接線分別往上跟往下連接，所以在線路設計上不會有太大的困難。
我們運用製程工具TSUPREM-4預先模擬為實作而設計的NDL run card，模擬出新SOI元件的結構，再以TMA TCAD對模擬出來的元件結構做I-V曲線的電性分析。從模擬之中我們得到幾個結論：○1多面閘極元件在VGS-Vth=0.7 V的時候，比單面閘極元件有著幾乎快要達到兩倍的電流驅動力；○2十字型閘極SOI MOSFET的臨限電壓、Ion/Ioff數值、次臨界因子幾乎跟四通道三面閘極SOI MOSFET一模一樣。
在製程上，十字型閘極SOI MOSFET具有比傳統SOI元件更簡化的隔離製程，此外我們還運用這樣的製程製作出了Leff ＝ 71nm的小尺寸元件。在電性方面，在Leff ＝ 71nm、Weff ＝ 440nm、tsi ＝ 120nm時，十字型閘極元件比具有相同的條件的四通道三面閘極元件具有較低的次臨界因子93.153、跟較高的Ion/Ioff比值1.66×10E5，而且沒有kink effect現象。因此，十字型閘極SOI MOSFET將比傳統SOI元件結構更適用於未來low power和high speed的超大型積體電路（ULSI）發展。

In this thesis, the Cross-Gate SOI MOSFET that has double sources and double drains was successfully fabricated. The new SOI device structure has five unique features. First, it uses mesa isolation instead of using conventional LOCOS and trench isolation to avoid the bird’s beak effect in LOCOS isolation and the complexity of digging trench in trench isolation； second, it has three surfaces of gate structures which can increase the effective channel width of the device to enhance the current drivability of the device without reducing the packing density of the circuit； third, it has four channels which can increase the current drivability of the device； fourth, it has narrowed source and drain that can reduce the leakage current； fifth, it has double sources and double drains that can design double or half current in the electric circuit by one device.
According to the simulation results of the TSUPREM-4 and TMA TCAD, the saturation drain current of the multi-gate SOI devices are almost double larger than that of the conventional SOI device as VGS - Vth = 0.7 V. And the threshold voltage、 Ion/Ioff and subthreshold factor of the Cross-Gate SOI device are almost the same with such of the Four Channels Multi-Gate SOI device.
As far as the fabrication process is concerned, the new SOI device has simpler isolation processes than that of the conventional one. In addition, the nano-devices that Leff ＝ 71nm was successfully fabricated. As concerning the electrical behavior, under the same condition of Leff ＝ 71nm, Weff ＝ 440nm, tsi ＝ 120nm, the Cross-Gate SOI device has the lower subthreshold factor which is 93.153 and the higher Ion/Ioff which is 1.66×10E5 than those of the Four Channels Multi-Gate SOI device, in addition, the Cross-Gate SOI device has no kink effect. So, it can be concluded that such the Cross-Gate SOI device presented is much more applicable to the development of low power and high speed ULSI in the nearest future.

第一章 緒論 1
第二章 模擬結果與討論 4
2.1 單一閘極、雙重閘極、三面閘極、四面閘極、
π型閘極SOI MOSFET元件的模擬與比較 4
2.2 單一通道閘極、單一通道三面閘極、四通道三面閘極、
十字型閘極SOI MOSFET元件的模擬與比較 9
2.3 結論 24
第三章 元件設計與製作 25
3.1 製作SOI層 25
3.2 製作Zero Mask 28
3.3 元件隔離及完成主動區 30
3.4 沉積Gate Oxide 37
3.5 完成閘極區域 37
3.6 形成源極跟汲極區域 44
3.7 製作Contact Hole 44
3.8 製作金屬層 45
第四章 實驗結果與討論 48
4.1 半導體元件參數量測說明與注意事項 48
4.2 IDS － VGS特性曲線的探討 49
4.3 IDS － VDS特性曲線的探討 57
4.4 結論 58
第五章 結論 59
參考文獻 60

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