類比數位轉換器在現今的混合系統中，是不可或缺的一環。本篇論文呈現了一個具有中等解析度與取樣速度，及低功耗的單斜率積分ADC，其適合前端生醫訊號紀錄的相關應用。本研究專注於簡化由外部輸入的控制訊號。此外，與先前發表的單斜率積分ADC相比，類比部分中的轉換器在功耗上亦有大幅度的改進。本設計利用台積電0.18μm製程技術實現於晶片上，以驗證10位元的解析度。在40k Hz的取樣頻率下，測得的功耗為18μW，晶片核心的面積為0.06mm2。

The analog-to-digital converter (ADC) is an essential component in modern mixed-signal system applications. This thesis presents the design and evaluation of a single-slope integrating ADC which features medium-resolution, medium-speed and low-power-consumption, suitable for application in a bio-signal acquisition front-end. The aim of this study is to simplify the external control signals and to reduce the power consumption of the analog part of the converter compared to previously reported single-slope integrating ADC. For practical evaluation the design was realized as a prototype in TSMC 1P6M 0.18μm CMOS technology proving 10 bit resolution. The measured power consumption is 18 μW when operating with 40 kHz sample-rate and the chip active area occupies 0.06 mm2

摘要 i
Abstract ii
Contents iii
List of Figures . v
List of Tables viii
Chapter 1 Introduction 1
1.1 Background and motivation 1
1.2 Contributions of this thesis 4
1.3 Thesis organization 7
Chapter 2 System design 8
2.1 ADC Specification 8
2.2 Single-slope conversion principle 9
2.3 System architecture 12
2.3.1 Register circuits 13
2.3.2 Internal clock generation 14
2.3.3 Voltage-to-time converter (VTC) 15
Chapter 3 Circuit Design 16
3.1 Counter circuit design 16
3.2 Register 19
3.3 Bias circuit tree 20
3.3.1 The internal bias source 22
3.4 Reset pulse generation 24
3.5 Voltage-to-time converter 25
3.5.1 Asymmetric OTA for clock gating 32
3.5.2 Clocked comparator 34
Chapter 4 Measured Results 36
4.1.1 Counter 37
4.1.2 On-chip bandgap reference circuit 38
4.1.3 Reset-pulse-generator 40
4.1.4 Voltage-to-time converter 41
4.3 Dynamic measurement 45
4.4 Comparison 47
Chapter 5 Discussion and Conclusions 50
5.1 Conclusions 53
5.2 Future work 54

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