本論文提出了管道快速傅利葉轉換處理器的一種新設計方法，管道快速傅利葉轉換處理器可以達到高生產率，而且對於那些要求快速傅利葉轉換可以處理連續進入的資料序列、樣本為一個接一個循序輸入的系統來說，是非常合適的設計架構。但是，對於採用單一延遲反饋方法設計的傳統管道快速傅利葉轉換處理器，則有著蝴蝶處理單元硬體使用效率低落的問題。除此之外，快速傅利葉轉換運算後的結果更是位元反向順序的輸出序列，這並不適合用於快速傅利葉轉換的一些應用如正交分頻多工。所以本論文提出了創新的管道快速傅利葉轉換設計架構，方法是先將輸入序列分成兩路資料流，再傳送到以向前饋送資料為交換單元基礎設計的快速傅利葉轉換處理器。這設計方法可以充分的運用蝴蝶運算單元，而讓加法器減少近一半的所需數量。雖然此架構在最後一級需要有一額外的大暫存器，但此一大暫存器可重新安排規劃並合併到排序輸出序列所需使用的暫存器中，這樣就能解決最後一級的額外大暫存器問題且也能得到正常順序的運算輸出。本論文採用新提出的架構設計方法來實作出8192點的快速傅利葉轉換處理器，另外也使用radix- 2^4演算法跟搭配特定的常數乘法器來實現 的複數乘法運算部份，這樣整個架構所要用到的複數乘法器數量就可以減至三組。在適當的資料分割和分配下，所有資料交換單元和排序輸出序列模組裡大量使用的暫存器，都可以改由多組使用單一埠的記憶體模組來替代而不會造成任何效能的降低。其他設計架構的顯著特點包括大幅減少旋轉因子所需儲存的個數，還有各級處理單元使用的資料表示位元長度有經過資料準確度的取捨，而不是無限制的增加位元長度或沒有標準的縮減位元長度。晶片實作使用TSMC 0.18 、1P6M CMOS製程，核心面積僅達8.74 ，對正常順序輸入和正常順序輸出的快速傅利葉轉換處理器來說，本論文所實作出的面積是最小的。

In this thesis, a new design methodology for pipeline FFT processor has been proposed. The pipeline FFT processor can achieve high throughput rate, and is very suitable for those systems where the continuous data sequences that call for the FFT processing enter systems sample by sample sequentially. However, the traditional pipeline FFT design based on the common single delay feed-back approach suffers low hardware utilization for the butterfly unit. In addition, the resulted transformed sequence is in the form of bit-reverse order which is not suitable for some FFT applications such as OFDM (Orthogonal Frequency Division Multiplexing). Therefore, this thesis proposes a novel pipelined FFT design by first splitting the input sequence into two data streams, which can then be applied to the FFT data-path based on the feed-forward dual-delay path data commutator. The resulted FFT architecture can achieve full butterfly utilization such that the required number of adders can be reduced by almost a half. One potential drawback of the proposed approach is that some additional large storage buffer is required at the last stage. However, the additional storage buffer can be re-organized and merged with the output reordering buffer together such that the normal-order transformed output sequence can be generated. The proposed approach has been applied to the design of 8-K point FFT in this thesis. The 8-K FFT architecture proposed in this thesis is designed based on the radix- 2^4 algorithm such that the required number of general complex number multipliers can be minimized to three. The multiplication of is realized by the dedicated constant multiplier architecture. By proper data partition and allocation, the large buffer required for many data commutator and the output reordering buffer can both be efficiently realized by multi-bank single-port memory modules. The other salient features of the 8-K FFT also include the table reduction for twiddle factors as well as the optimized variable internal data representation. The proposed FFT processor has been implemented by the TSMC 0.18um 1P6M CMOS process technology with core area of 8.74 which is the smallest design reported in the literature for normal sequential input/output order FFT.

目錄
第1章 簡介 1
1.1 研究動機 1
1.2 論文架構 2
第2章 快速傅利葉轉換演算法 3
2.1 Radix-2 FFT 3
2.2 Radix-4 FFT 7
2.3 Radix-8 FFT 8
2.4 不同演算法之比較總結 10
第3章 快速傅利葉轉換硬體架構 11
3.1 資料回饋架構 12
3.2 資料前饋架構 15
3.3 結論與比較 18
第4章 快速傅利葉轉換電路實現 20
4.1 提出的資料前饋架構及其他電路架構的設計 21
4.2 8192點FFT實作架構及資料位元長度分析 33
4.3 結論與比較 41
第5章 實驗結果 43
第6章 未來工作 50
參考文獻 51
附錄 55

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