本論文提出一個簡易的晶片內自動頻率調協電路。這個調協電路是改善自電壓控制濾波器頻率調協電路。我們把電壓控制濾波器以單一時間常數電路代替。
這個單一時間常數電路可以產生一個可控制的延遲時間時脈。這個調協電路依靠和參考時脈之間固定的延遲時間來調協濾波器的頻寬。單一時間常數電路的設計是非常容易的。因為比較簡單的電路,這個電路有較小的晶片面積和較低的能量損耗。
這個電路使用0.35μm CMOS 製程製作晶片，其供應電壓為±1.5 V。模擬結果顯示，這個頻率調協電路的頻寬誤差小於12%和電壓消耗小於9mW，在供應電壓變動±10%，操作溫度(-20℃到70℃)和五種SPICE製程模組的情況下。

In this thesis, a simple on-chip automatic frequency tuning circuit is presented. The tuning circuit is improved from voltage-controlled filter (VCF) frequency tuning circuit. We use a single time constant (STC) circuit to substitute the voltage-controlled filter.
The STC circuit can produce a controllable delay time clock. The tuning circuit uses the constant delay time to tune the frequency of the filter. The design of a STC circuit is easy. Because the circuit is simple, the tuning circuit has less chip area and less power consumption.
The circuit has been fabricated with 0.35μm CMOS technology. It operates with supply voltages ±1.5 V. The filter operates at a 3-dB frequency of 10MHz. In simulation, the frequency tuning circuit has a 3-dB frequency tuning error of less than 12% and the power consumption less than 9.05mW over a range of supply voltages (±10%), operating temperatures (-20℃ to 70℃) and five models of SPICE model.

Abstract (Chinese) i
Abstract (English) ii
Contents iii
List of Figures vi
List of Tables viii
Chapter 1
Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 3
Chapter 2 Previous Tuning Methods 4
2.1 The Automatic Frequency Controller 4
2.2 Frequency Tuning Circuit 6
2.2.1 Sinusoidal Oscillator Based PLL Frequency Tuning 6
2.2.2 Relaxation Oscillator Frequency Tuning Circuit 8
2.2.3 Voltage-Controlled Filter Frequency Tuning Circuit 10
2.2.4 PLL with Charge-Pump Phase Comparator 12
Chapter 3 The Proposed Tuning Circuit and the Gm-C Filter 13
3.1 The Operation of Proposed Tuning Mechanism 13
3.1.1 The Block Diagram of Tuning Circuit 13
3.1.2 STC Circuit 14
3.1.3 Delay Time Analysis 15
3.1.4 The Tunable OTA 19
3.2 The Proposed Tuning Circuit 22
3.2.1 Voltage Comparator 23
3.2.2 Phase Detector 28
3.2.3 Charge Pump 29
3.2.4 Low-Pass Filter 30
3.3 Filter Design 31
3.3.1 Basic Filter Theorem 31
3.3.2 The Gm-C Filter 32
3.3.2.1 OTA’s Simple Circuit 32
3.3.2.2 Gm-C Low-Pass Filter 34
Chapter 4 Simulation and Measurement Result 37
4.1 Simulation Result 37
4.1.1 Gm-C Filter Simulation Result 38
4.1.1.1 Without Automatic Tuning Circuit 38
4.1.1.2 With Automatic Tuning Circuit 39
4.1.1.3 Bias Adjust 40
4.2 Measurement Result and Layout 42
4.2.1 Chip Features and Layout 42
4.2.2 Measurement Result 44
Chapter 5
Conclusions 47
Reference 49

[1] Tsividis, Y.P.; "Integrated continuous-time filter design - an overview", IEEE Journal Solid-State Circuits, Volume 29, Issue 3, pp. 166 - 176, March 1994.
[2] Abo, A.M.; Gray, P.R.; " A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter", IEEE Journal Solid-State Circuits, Volume 34, Issue 5, pp. 599 - 606, May 1999.
[3] Maurer, L.; Schelmbauer, W.; Pretl, H.; Adler, B.; Springer, A.; Weigel, R.; "On the design of a continuous-time channel select filter for aZero-IF UMTS receiver", IEEE Conference Vehicular Technology , Volume 1, pp. 650 - 654, May 2000.
[4] Durham, A.M.; Redman-White, W.; Hughes, J.B.; "High-linearity continuous-time filter in 5-V VLSI CMOS", IEEE Journal Solid-State Circuits, Volume 27, Issue 9, pp. 1270 – 1276, Sept. 1992.
[5] Silva-Martinez, J.; Steyaert, M.S.J.; Sansen, W.; "A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning ", IEEE Journal Solid-State Circuits, Volume 27, Issue 12, pp. 1843 - 1853, Dec. 1992.
[6] Teo, T.H.; Khoo, E.-S.; Uday, D.; "Fifth order low-pass transitional Gm-C filter with relaxation oscillator frequency tuning circuit", IEEE Conference Electron Devices and Solid-State Circuits, pp.229 - 232, Dec. 2003.
[7] Johns, D.; Martin, K.; "Analog integrated circuit design", John Wiley & Sons on Canada, 1997.
[8] Szczepanski, S.; Koziel, S.; "A 3.3 V linear fully balanced CMOS operational transconductance amplifier for high-frequency applications" IEEE Conference Circuits and Systems for Communications, pp. 38 - 41, June 2002.
[9] Traff, H.; "Novel approach to high speed CMOS current comparators", Electronics Letters, Volume 28, Issue 3, pp. 310 - 312, Jan. 1992.
[10] Hung Tien Bui; Al-Sheraidah, A.K.; Yuke Wang; "New 4-transistor XOR and XNOR designs", IEEE Asia Pacific Conference ASICs, pp. 25 - 28, Aug. 2000.
[11] Rhee, W.; "Design of high-performance CMOS charge pumps in phase-locked loops", IEEE International Symposium Circuits and Systems, Volume 2, pp.545 - 548, June 1999.
[12] Su, K.; "Analog Filters", Second Edition, Kluwer Academic Publishers, 2001.
[13] Tsividis, Y.P; "Design considerations for high-frequency continuous-time filters and implementation of an antialiasing filter for digital video", IEEE Journal Solid-State Circuits, Volume 25, Issue 6, pp.1368 – 1378, Dec. 1990.