傳統低階封裝產品主要應用於消費性電子產品及通訊設備，訊號之傳輸是藉由金線連接積體電路產品IC 與導線架內腳，再透過導線架(釘架)外腳與電路板作接合。然而，先進封裝產品的發展與產品功能的多樣化，導致傳統封裝產品之競爭力降低。因此，透過降低封裝成本、擴大封裝面積以提昇產品競爭性及提昇產能為目前首要工作。
本論文主要探討導線架(釘架)設計由小矩陣轉為大矩陣之可行性及克服、解析所面臨之問題，並尋求解決之方法。當導線架材料從小矩陣轉為大矩陣設計可增加每條釘架之產品顆數且有利於封裝製程之單位時間之產出(UPH)。然而,因產品顆數增加也導致釘架停留於銲線機台之時間增長，因此釘架之耐熱強度備受考驗,所面臨之最大難題為釘架之銅介面層剝離，在改變釘架預熱時間後分析得解決銅介面層剝離之難題。
本論文研究包含釘架設計之發展、封裝機台作業能力之評估、實務驗證及導入流程及所遇問題解析。由本論文高密度導線架封裝解決方案研究得知可降低生產成本 13~40%及提高產能10~44%.

Majority of traditional assembly packaging are applied in consumer electronics and communication products. Electrical signals are transmitted through gold wire connecting IC and inner leadframe. The assembled product is then mounted to PCB board via outer lead. However, products with complicated functions require new development on advanced IC packaging solution that makes low market demand for traditional process. Therefore, assembly package cost reduction is the first target to keep the advantages of the products and make it profitable.
In this thesis, the feasibility on leadframe design from small matrix (2 row) to large matrix was analyzed making high volume throughput by increasing the totally unit quantity in one strip leadframe. With the introduction of the new strip outline dimensions, the staging time increases at wire bonder machine resulting to copper layer delamination. Appropriate control on the preheat temperature resolved the copper layer delamination issue. Assembly package for large leadframe design was then proposed and the capacity of machine was surveyed. The benefit of product cost saving and the increase on assembly yield for the enlarged leadframe are evaluated accordingly.

致謝
中文摘要
Abstract
Contents
Abbreviations
Figures captions
Table captions
Chapter 1.Introduction
Chapter 2. New Matrix Leadframe Design proposal
Chapter 3. Experiment
3-1 Material preparation and test condition
3-2 Scanning acoustic microscope inspection introduction
3-3 Experiment result
3-4 Assembly problem
Chapter 4. Improvement
Charter 5. Summary
References
附錄

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