金氧半場效電晶體為積體電路的核心元件，廣泛地應用在各種電子產品上。為改善電晶體的操作特性，可以利用電晶體尺寸的微縮、高介電閘極絕緣層材料、以及應變矽通道等方式，來增加電晶體的驅動電流，以及切換速度。然而電晶體尺寸的微縮，須克服微影技術與成本的問題，此外，電晶體會面臨嚴重的短通道效應、以及閘極漏電流等問題。而high-κ閘極絕緣層仍有載子缺陷、聲子散射、偶極引起的臨界電壓調控等問題須克服。本論文則研究金氧半場效電晶體在外界機械應力作用下的特性，在機械應力作用下通道會產生應變，電晶體的載子遷移率、驅動電流、以及切換速度會因此增加。研究項目包含半導體製程所產生的應變矽、外界機械應力作用下所產生的應變矽、以及應變矽在高/低溫環境下的元件特性。除了電性量測與機制分析，我們亦利用半導體製程模擬軟體來研究電晶體在應力作用下的特性。
首先，我們利用氮化矽覆蓋在n型金氧半場效電晶體上的方式，將應力施加到電晶體通道，矽晶格受到應變後，載子移動率會隨之增加，可提升電晶體元件的操作速度。第二部份，則是在n型金氧半場效電晶體之通道方向引入外界機械應力，研究電晶體在外界應力作用下的特性。利用製程來產生應變，除了應力，元件特性也會受到製程因素的影響。因此，在本單元中，我們設計一種獨特的應變技術來做研究。第三部份，我們研究應變矽在不同環境溫度下的元件特性。最後，我們研究超薄閘極氧化層在應變矽中的漏電流問題。

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are major devices inintegrated circuit, extensively used in various electronic products. In order to improve the electrical characteristics, scaling channel width and length, using high-κ gate dielectric insulator, and strained silicon may be utilized to increase the driving current and circuit speed. Nevertheless, the scaling of the channel width and length must overcome the limitation of the photolithographytechnology and cost. Once the method is employed, the MOSFETs will face a serious short-channel effect and gate leakage current. In the aspect of high-κ gate dielectric insulator, there still have problems, containing the trap states, phonon scattering, dipole-induced threshold voltage variation, needed to be solved. This dissertation focuses on the properties of MOSFETs experienced an external-mechanical strain, where the channel will be strained. Hence, the mobility, driving current, and circuit speed will increase. Our research can be divided into three topics: fabricating process-induced strained Si, external mechanical stress-induced strained Si, and the properties of strained Si MOSFETs at different temperatures. Except the electrical measurement, we also used the ISE-TCAD to simulate the electrical characteristic of MOSFETs under stress.

Firstly, we apply the stress on n-MOSFETs by utilizing the nitride-capping layer. Once the lattice is strained, the mobility will increase, hence resulting in the operating speed. Secondly, the electrical characteristics under external stress is explored by introduced the external mechanical stress along the channel length of nMOSFETs. In addition to the fabricating process-induced strain, the fabricating process condition will also influence the device characteristics. As a result, we propose a new strain technology for our following research. Thirdly, the device performance of strained Si under different temperatures is investigated. Finally, we discuss the gate leakage current in strained Si depending on the ultra-thin gate oxide layer.

Chinese Abstract I
English Abstract II
Acknowledgement IV
Contents V
Figure Captions XV
Table Captions VII
Chapter 1Introduction 1
1.1 General Background 1
1.1.1 Overview of Strained Si MOSFETs 1
1.1.2 Uniaxial Tensile Strained Si MOSFETs 1
1.2 Motivation 2
Chapter 2STD and LMCDevices with (100)/<100>Surface Orientation/Current Direction Introduction 5
2.1 Motivation 5
2.2 Experimental Procedures 6
2.3 Results and Discussion 7
Chapter 3Proposed External Mechanical Stress Methods 19
3.1 Motivation 19
3.2 Experimental Procedures 20
3.3 Results and Discussion 21
3.3.1 σ//L//J//<100>, STD Devices 21
3.3.2 σ//L//J//<100>, LMC Devices 25


Chapter 4High Temperature Effect 46
4.1 Motivation 46
4.2 Experimental Procedures 47
4.3 Results and Discussion 47
Chapter 5Low Temperature Effect 58
5.1 Motivation 58
5.2 Experimental Procedures 59
5.3 Results and Discussion 59
Chapter 6Low Temperature Behaviors of Electron Tunneling Currents through Ultrathin Gate Oxides in Strained nMOSFETs 73
6.1 Motivation 73
6.2 Experimental Procedures 74
6.3 Results and Discussion 75
Chapter 7Dependence of Electric Properties of n-MOSFETs Devices on Directions of Uniaxial Mechanical Strain and Current 89
7.1 Motivation 89
7.2 Results and Discussion 91
7.2.1 σ//L //J//<100>, STD Devices 91
7.2.2 σ//L //J//<100>& σ//L //J//<110> , STD Devices 92
7.2.3 J//<110>σ//L &σ//W , STD Devices 94
7.3 Conclusion 96
Chapter 8Conclusion 102
References 104
Biography 111
Publication List 112


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Chapter 2
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[5-8] 半導體元件物理施敏著

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[6-6] W. Zhao, “Opposing Dependence of the Electron and Hole Gate Currents in SOI MOSFETs Under Uniaxial Strain”, IEEE Electron Device Lett. vol.26, 410 _2005.
[6-7] Opposing Dependence of the Electron and Hole Gate Currents in SOI MOSFETs Under Uniaxial Strain, IEEE Electron Device Lett.vol. 26, no. 6, pp.410-412, June 2005.
[6-8] Nian Yang, A Comparative Study of Gate Direct Tunnelingand Drain Leakage Currents in N-MOSFET’s with Sub-2-nm Gate Oxides, IEEE Trans. Electron Devices, vol. 47, no. 8, pp.1636-1644, august 2000
[6-9] Kaushik Roy, Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits, Proceedings of the IEEE, vol. 91, no. 2, pp.305-327, February 2003.
[6-10] K. N. Yang, Characterization and Modeling of Edge DirectTunneling (EDT) Leakage in Ultrathin Gate Oxide, IEEE Trans. Electron Devices, vol. 48, no. 6, pp. 1159-1164, June 2001.

Chapter 6
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[7-2] J. L. Hoyt,IEDM Tech. Dig., 2002, pp. 23–26.
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[7-4] E. Scott, IEEE Trans. Electron Devices, vol. 51, pp. 1790-1797, 2004.
[7-5] A. Hamada, IEEE Trans. Electron Devices, vol. 38, pp. 895-900, 1991.
[7-6] C. Gallon, IEEE Trans. Electron Devices.,Devices, vol. 51, 1254, 2004.
[7-7] H. Irie,IEDM Tech. Dig., 2004, pp. 225-228.
[7-8] Mei-Na Tsai, Electrochemical and Solid-State Letters, Vol. 9, 2006.
[7-9] A. Shimizu, IEDM 01-433,19.4.1,(2001)
[7-10] G. L. Bir and G. E. Pikus, “Symmetry and Strain-Induced Effects in Semiconductors”, New York: John Wiley & Sons, 1974.
[7-11] I. Goroff and L. Kleiman, Phys. Rev.,vol. 132, pp. 1080-1084, 1963.
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[7-13] F. Stern, Phys , Rev. B, vol. 5, pp. 4891-4899, Dec. 1972.
[7-14] K. OHE,IIEEE Trans. Electron Devices.,Devices,36. no. 6,1110-1116, 1989.

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