在本篇論文中，我們將針對嵌入式系統越來越複雜，架構規格時常更新改變，整合困難且耗時，產品的生命週期越來越短等特性，提出一嵌入式系統硬體發展環境；以嵌入式系統硬體平台架構為基礎，依各種不同的應用，快速的整合出所需要的嵌入式系統硬體。此硬體發展環境主要是建構在一On-Chip Bus的平台之上，藉由此平台架構的彈性，一些模組可重覆使用，可參數化特性，加速整合時程，並快速完成系統驗證，達到time to market的目的。並且藉由發展此嵌入式系統硬體平台架構，討論及說明一嵌入式系統硬體的系統整合方式。將Verification Reuse的觀念導入系統驗證中，縮短系統驗證的時間。

In this paper, we proposed a hardware development environment of the Embedded system to reduce the complexity of the Embedded system archeitecture, fit the varied specification, decrease the difficulties and time consuming on hardware integration, and short the life period of products. According to the On-Cihp Bus platform, we can utilize certain modules repeatly and recofigure the parameters flexibily to integrate the necessary system hardware and complete the system verification rapidly that we can achieve the time to market. In this thesis, we discuss architecture of hardware platform and the technique of system integration. Further more; we introduce the concept of VRM (Verification Reuse Methodology) on the system verification that reduces the verification time of system.

1 論文簡介 1
1.1 研究動機 1
1.2 研究方法 2
2 相關研究探討 5
2.1 目前主要的ON-CHIP BUS 介紹 5
2.1.1 AMBA簡介 5
2.1.2 IBM CoreConnect Bus 簡介 6
2.1.3 PALMCHIP的CoreFrame Bus 簡介 7
2.1.4 Silicore的WISHBONE Interconnect Bus簡介 8
2.1.5 VSIA (Virtual Socket Interface Alliance) On-Chip Bus簡介 9
3 AMBA平台架構實作 10
3.1 AMBA元件之實作 10
3.1.1 AHB Bus Overview 10
3.1.2 AHB Bus Master BIU (Bus Interface Unit) 11
3.1.3 AHB Bus Slave BIU (Bus Interface Unit) 16
3.1.4 Arbiter & Decoder 21
3.1.5 APB Bus Overview 23
3.1.6 APB Bus Master & Slave BIU (Bus Interface Unit) 23
3.2 其他周邊及I/O 25
3.2.1 Interrupt Controller 25
3.2.2 UART (Universal Asynchronous Receiver & Transmitter) 27
3.2.3 Mctrl (Memory Controller) 29
3.2.4 LCD Controller 32
3.2.5 Keyboard Interface 33
4 系統整合(SYSTEM INTEGRATION) 34
4.1 系統整合流程概述 34
4.2 整合的規劃及設定 36
4.3 AMBA匯流排介面設計 40
5 系統整合驗證 45
5.1 AMBA驗證 46
5.1.1 利用LEON testbench 驗證 46
5.1.2 Bus Model (Bus-functional Model) & Protocol checker 51
5.2 各子系統整合驗證 54
5.2.1 子系統1整合驗證 54
5.2.2 子系統2整合驗證 56
5.2.3 子系統3整合驗證 58
5.2.4 子系統4整合驗證 60
5.2.5 子系統5整合驗證 62
5.3 韌體整合驗證 65
5.4 實作結果 67
5.4.1 合成結果 67
5.4.2 FPGA之實作 68
6 未來展望(FUTURE WORK) 70
6.1 整合SYS32-TME (ARM9TM LIKE)至AMBA平台中 70
7 結論(CONCLUSION) 75
8 參考文獻(REFERENCE) 76
9 APPENDIX (AMBA PLATFORM IP DELIVERABLE) 77
9.1 INSTALLATION GUIDE 77
9.1.1 File Structure 77
9.1.2 File Description 78
9.2 RTL SIMULATION AND VERIFICATION 83
9.2.1 How To Simulation 83
9.2.2 RTL Verification 85
9.3 SYNTHESIS 86
9.3.1 Synthesis Environment 86
9.3.2 Synthesis Steps 86
9.4 GATE LEVEL SIMULATION 88
9.4.1 Simulation Environment 88
9.4.2 How To Simulation 89
9.4.3 Verification 90

[1] A. Sangiovanni-Vincentelli and G. Martin, “Platform-Based Design and Software Design Methodology for Enbedded Systems”, IEEE Design & Test of Computers, Vol. 18, pp. 23-33, Nov. 2001.
[2] Steve Furber, ARM System-on-Chip Architecture, 2nd Edition, Addison-Wesley.
[3] M. Hunt and J. A. Rowson, “Blocking in A System On a Chip”, IEEE Spectrum, Vol. 33, pp. 35-41, Nov. 1996.
[4] J. Haase, T. Oberthur, and M. Oberwestberg, “Design Methodology for IP Providers”, Proceeding of Design, Automation and Test in Europe Conference and Exhibition, pp. 49-61, Germany, Mar. 1999.
[5] W. Remaklus, “On-Chip-Bus Structure for Custom Core Logic Design”, Technical Report, IBM Microelectronics, 1998.
[6] P. Lysaght, R. Chapman, and T. Durrani, “System Level Integration, Intellectual Property, and the Education of a New Generation of System Designers”, IEE Colloquium on Systems on a Chip, Vol. 2, pp.1-5, 1998.
[7] AMBA Specification, Rev. 2.0, ARM Inc, 1999.
http://www.arm.com/armtech/AMBA_Spec?OpenDocument.
[8] ARM7TDMI Technical Reference Manual, Rev. 3, ARM Inc, 2001.
http://www.sharpsma.com/sma/products/mcu/mcu_files/ARM7TDMI_TRM.pdf.
[9] K. Michael and B. Pierre, Reuse Methodology Manual-For System-On-a-Chip Designs, 2nd Edition, Kluwer Academic, Kluwer Academic Publishers, 1999.
[10] ARM PrimeCell Technical Reference Manual, Rev. B, ARM Inc, 2002.
http://www.arm.com/techdocs/5EJF4G/$File/DDI0181C_Errata01.pdf?OpenElement.
[11] Verification Reuse Methodology-AMBA Verification IP, Cadence Inc, 2002.
http://www.cadence.com/whitepapers/VRMethodology.html#theneed.
[12] LEON/AMBA VHDL model description, Rev. 2.2, Gaisler Research Inc., Nov. 2000.
http://www.estec.esa.nl/wsmwww/leon/leonvhdl-2.2.pdf.
[13] Overview of the CoreFrame Architecture, Rev. 1.01, Palmchip Inc., Jan. 2002.
http://www.palmchip.com/pdf/CP-9152W-1.01.pdf.
[14] Virtual Socket On-chip Bus Attributes Specification, Rev. 0.9.6, VSIA Org., 1999.
http://www.vsi.org/library/pressrelease/081798.pdf.
[15] WISHBONE Specification, Rev. B.2, Silicore Inc., Oct. 2001.
http://www.silicore.net/pdfiles/wishbone/specs/wbspec_b2.pdf.
[16] S. Simon, “The ARM9 Family – High Performance Microprocessors for Embedded Applications”, Proceeding of IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 230-235, Oct. 1998.