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博碩士論文 etd-0125105-004356 詳細資訊
Title page for etd-0125105-004356
論文名稱
Title
ANT單元管線式前看進位加法器的低功率設計與植入式神經電刺激之小面積數位類比轉換器
Low Power Design of an ANT-based Pipelining CLA and a Small DAC Used in an Implantable Neural Stimulator
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
71
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2005-01-19
繳交日期
Date of Submission
2005-01-25
關鍵字
Keywords
低功率、時脈產生電路、前看進位加法器、植入式神經電刺激
carry-lookahead adder, clock generator, low power, implantable neural stimulator
統計
Statistics
本論文已被瀏覽 5639 次,被下載 19
The thesis/dissertation has been browsed 5639 times, has been downloaded 19 times.
中文摘要
本論文包含兩個主題,第一個主題是ANT邏輯單元實現的低功率八位元管線式前看進位加法器。第二個主題是植入式神經電刺激之小面積數位類比轉換器。
ANT邏輯單元實現的低功率八位元管線式前看進位加法器,利用雙相位之全N電晶體下拉方塊,以程式邏輯陣列形式,配合管線化的資料偵測,來實現高速與低功率的八位元前看進位加法器。在N電晶體計算電路與輸出值之間加入兩個回饋式電晶體可以加速程式邏輯陣列加法器的充電與放電速度。使用時脈控制電路與時脈產生電路都可以偵測資料變化,優點是當資料輸入在連續運算內如果沒有變化,使時脈維持在高電位,運算單元的資料處理與計算狀態可自動關閉,因而使功率下降。本設計保留高速的優點,同時加入低功率的效果。
植入式神經電刺激器以電流刺激輔助患者重建神經信號的傳遞路徑,因此我們提出一個植入式神經電刺激器的小面積數位類比轉換器,用以產生刺激電流。本設計除了減少電晶體數量來降低晶片面積與功率,並且改良線性度與增加電流最大輸出值,使其成為能被實際應用的電路。
Abstract
This thesis includes two topics. The first topic is a low power design of 8-bit ANT-based pipelining CLA. The second one is a small digital to analog converter (DAC) used in an implantable neural stimulator.
An ANT-based low-power 8-bit pipelining carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by two feedback MOS transistors between the evaluation NMOS blocks and the outputs. Both the added power-aware clock control circuit and clock generation circuit detecting data transition take advantage of shutting down the processing stages given identical inputs in two consecutive operations by keeping high clock level. The design keeps the advantage of high speed while having the effect of low power dissipation.
The implantable neural stimulator assists patients to reconstruct transmission paths of neural signals by current stimulation. The proposed small DAC not only decreases the chip area and power dissipation by reducing transistor count, but also improves the linearity with higher current output performance. All of measured performances of the proposed DAC make the chip worthy of being implemented in a field application.
目次 Table of Contents
摘要 i
Abstract ii
第一章 簡介 1
1.1 論文動機  1
1.2 先前文獻探討  2
1.2.1 前看進位加法器  2
1.2.2 植入式神經電刺激之數位類比轉換器  3
1.3 論文大綱  4
第二章 ANT單元管線式前看進位加法器的低功率設計 5
2.1 概論  5
2.2 原理概述  6
2.3 架構與原理說明  6
2.3.1 ANT邏輯單元  6
2.3.2 前看進位加法器設計  8
2.3.3 PLA管線式電路  10
2.3.4 時脈控制電路  12
2.3.5 時脈產生電路  17
2.4 分析  20
2.4.1 速度分析  20
2.4.2 面積分析  24
2.4.3 功率分析  28
2.5 電路的模擬與量測  29
2.5.1 模擬結果  29
2.5.2 量測結果  31
第三章 植入式神經電刺激之小面積數位類比轉換器   38
3.1 功能性電刺激的原理與應用  38
3.2 植入式神經電刺激的系統電路架構  41
3.2.1 系統電路架構  41
3.2.2 混合信號模組  41
3.3 小面積數位類比轉換器  43
3.3.1 電路設計  43
3.3.2 設計與佈局考量  44
3.3.3 模擬結果  47
3.3.4 架構比較  52
3.4 量測結果 52
第四章 結論 55
參考文獻 57
參考文獻 References
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