本篇論文主旨在利用標準 0.18um CMOS 製程設計應用於超寬頻系統前端
接收器之低雜訊放大器。此低雜訊放大器是以兩級放大為主架構，第一級為電感
退化性架構，是為了增加頻寬以及輸入端阻抗匹配，第二級為傳統的CS架構，可以增加順向增益(S21)，輸出端匹配是使用LC-section。為了改善高頻增益，在第一級與第二級中間利用series-peaking的方法去實現。在第二級與輸出端中間利用回授電阻改善其輸出匹配以及整體電路穩定度。我們所設計的低雜訊放大器，供應電壓VDD為1.5伏特，整個電路消耗功率約為16.5mW，及整個電路大小約為920*940mm2。本研究的低雜訊放大器所模擬的規格，S11為 -9dB以下，S22為 -10dB以下，順向增益(S21)在3.1-10.6GHz時為11.63dB~12.56dB，逆向隔離(S12)為 -32dB以下，而雜訊指數為3.3dB~3.96dB。

The objective of this thesis is aimed at the design of low noise amplifier (LNA) for
an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process.
A two amplified stage topology is proposed in the low noise amplifier. The first stage
introduces inductively source degeneration, it can achieve wideband
input impedance matching. The second stage introduces traditional CS configuration, it can
improve the forward gain (S21). The second stage also used L-C section for output match.
In order to improve the gain at high frequency, we introduces the series peaking between the
first stage and second stage. We use the resistive-feedback between second stage and output, it can achieve wideband output impedance matching. The total power dissipation of the low noise amplifier is about 16.5mW at power supply 1.5 volt and the chip size is 920*940mm2. The simulated result shows that S11 is under -9dB, S22 is under -10dB, the forward gain S21 is 11.63dB~12.56dB at 3.1-10.6GHz, the reverse isolation S12 is under -32dB, and the noise figure is3.3dB~3.96dB.

Contents
摘要 I
Abstract II
Contents III
List of Figure V
Chapter 1 Introduction 1
1.1 Ultra-Wideband Communication System 1
1.2 Motivation 2
1.3 Thesis Organization 4
Chapter 2 Low Noise Amplifier Design 5
2.1 Introduction 5
2.2 Consideration in Low Noise Amplifier 6
2.2.1 Impedance Matching 6
2.2.2 Stability 10
2.3 Low Noise Amplifier Topology 12
2.3.1 Basic Topologies of Low Noise Amplifier 12
2.3.2 Inductively source degeneration LNA Noise Analysis 16
2.4 Shunt-Peaked Architecture 20
2.5 Recent Wide-Band LNA Design 23
Chapter 3 The proposed CMOS LNA for 3.1-10.6GHz Ultra-Wideband 28
3.1 Circuit topology 28
3.1.1 Input match 30
3.1.2 Series peaking 32
3.1.3 Resistive feedback 35
3.1.4 Gain Analysis 39
Chapter 4 Simulation Results and Discussion 41
Chapter 5 Conclusion 49
Reference 50

List of Figure

Chapter 1 Introduction
Figure 1-1 Multiband spectrum allocation 2
Chapter 2 Low Noise Amplifier Design
Figure 2-1 Block diagram of a basic radio receiver 5
Figure 2-2 A lossless network matching the load impedance to a transmission line [7] 7
Figure 2-3 Block diagram of a microwave amplifier [8] 8
Figure 2-4 The eight possible impedance-matching networks with two reactive components [8] 8
Figure 2-5 Effect of adding series and shunt reactive components in the Smith Chart [8] 9
Figure 2-6 Stability of two-port networks [8] 11
Figure 2-7 Resistive termination 12
Figure 2-8 termination 13
Figure 2-9 Shunt-series feedback 14
Figure 2-10 Inductively source-degeneration 15
Figure 2-11 Cascode LNA architecture 16
Figure 2-12 Small-signal model for LNA noise model [11] 16
Figure 2-13 Shunt-peaked amplifier 21
Figure 2-14 Model of shunt-peaked amplifier 22
Figure 2-15 Shunt-feedback wideband LNA 24
Figure 2-16 Small-signal equivalent circuit at the input 24
Figure 2-17 Common-gate wide-band LNA 26
Figure 2-18 Chebychev band-pass filter 26
Figure 2-19 The LNA with Chebychev filter configuration 27

Chapter 3 The proposed CMOS LNA for 3.1-10.6GHz Ultra-Wideband
Figure 3-1 Proposed UWB LNA schematic 29
Figure 3-5 Proposed UWB LNA with series-peaking 33
Figure 3-6 A common-source amplifier with series peaking and drain parasitic capacitance 33
Figure 3-7 Gain compare with series peaking 34
Figure 3-8 UWB LNA with resistive feedback 35
Figure 3-9 Small-signal equivalent circuit model without 36
Figure 3-10 Voltage reflection conefficient without 36
Figure 3-11 Small-signal equivalent circuit model with 37
Figure 3-12 Voltage reflection conefficient with 38

Chapter 4 Simulation Results and Discussion
Figure 4-1 The inductor with guard-ring 42
Figure 4-3 S22 Simulation 43
Figure 4-4 S21 Simulation 44
Figure 4-5 NF Simulation 44
Figure 4-6 S12 Simulation 45
Figure 4-7 Stability Simulation 45
Figure 4-8 Simulation 46
Figure 4-9 Simulation 46

List of Table
Chapter 3 The proposed CMOS LNA for 3.1-10.6GHz
Table 3.1 Series peaking summary 34

Chapter 4 Simulation Results and Discussion
Table 4.1 Simulated performance list of UWB LNA 47
Table 4.2 Comparison of broadband LNA performance 47

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