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博碩士論文 etd-0125111-164403 詳細資訊
Title page for etd-0125111-164403
論文名稱
Title
雙線性二階積分帶通濾波器
Bilinear Second Order Integral Bandpass Filter
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
56
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2011-01-21
繳交日期
Date of Submission
2011-01-25
關鍵字
Keywords
雙取樣、雙線性、改良式、積分器、濾波器
Filter, integrator, Modified, double sampling, bilinear
統計
Statistics
本論文已被瀏覽 5717 次,被下載 774
The thesis/dissertation has been browsed 5717 times, has been downloaded 774 times.
中文摘要
傳統積分器的轉換函數有嚴重的高頻彎曲效應,這不利於製作高頻率波電路,在參考文獻[1]當中提到一個新的轉換函數可以大幅改善這個誤差,但是我們卻發現到原電路的設計不符合這個轉換函數。
本論文提出一個不同的積分器架構,是採用雙取樣的方式來實現這改良式的雙線性轉換函數,除此之外,我們還加入能夠降低輸入阻抗的閘極接地放大器以及減少電荷注入誤差的虛擬開關技術,最後再用此核心電路組成二階帶通濾波器。

本研究採用Hspice來模擬此濾波電路以及設計佈局的格式,再使用0.35μm製成製作晶片。取樣頻率為10MHz、中心頻率為1MHz、功率消耗為1.78mW.
Abstract
Traditional transfer function of integrators have warping effect in high frequency, this isn’t good for make filter circuit. In reference[3] they mention a new transfer function to improve this error, but we found that the design of the previous circuit doesn’t conform to the new transfer function.
In this thesis, a different structure of integrator is presented, it use the method of double sampling to realize the modified bilinear transfer function, in addition, we also add a grounded-gate amplifier to decrease the input impedance and dummy switch technique what can reduce the charge injection error, then we use the central circuit to make the second order bandpass filter.
The proposed circuit employ Hspice to simulate and design the form of the circuit layout, then use TSMC 0.35μm CMOS process to make chip. The sampling frequency is 10MHz, the central frequency is 1MHz, and the power consumption is 1.78mW.
目次 Table of Contents
Contents

Chapter 1 Introduction 1
1-1 Background 1
1-2 Motivation 2
1-3 Thesis Organization 3
Chapter 2 The Switched-Current (SI) Technique and The Previous Circuit 4
2-1 Sample and Hold principle 4
2-2 Switched-Current Technique 4
2-3 Non-ideal Behavior 7
2-3-1 Mismatch 7
2-3-2 Transmission error 8
2-3-3 Clock Feedthrough (CFT) error 10
2-3-4 Noise 13
2-4 Delay Cell 15
2-5 SI Technique’s advantage and shortcomings 16
2-6 The previous circuit 17
Chapter 3 The Proposed Filter Circuit 19
3-1 The Second Order Integral Band Pass Filter 19
3-2 Design of The Bilinear Integrator 20
3-2-1 Transform of The Integrator 21
3-2-2 Build the architecture 23
3-3 Compensation Method 27
3-3-1 Dummy Switch 27
3-3-2 Grounded-Gate Amplifier 28
3-4 The Current Amplifier 30
3-5 The Bandpass Filter Design 31
Chapter 4 Simulation and Measurement Results of the Proposed Bilinear Second Order Integral Filter 36
4-1 Implementation, Specifics and Layout of The Circuit 36
4-2 Simulation and Measurement Result 42
Chapter 5 Conclusion 46
Reference 47

List of Figures and Tables

Figure 2.1 Current mirror circuit. 4
Figure 2.2 First generation SI memory cell. 5
Figure 2.3 Second order Si memory cell. 6
Figure 2.4 Diagram of mismatch 7
Figure 2.5 Transmission error 9
Figure 2.6 Diagram of overlap capacitance 10
Figure 2.7 Diagram of channel charge redistribution 11
Figure 2.8 Noise power spectrum of typical MOS 13
Figure 2.9 Delay cell 15
Figure 2.10 Timing diagram for the delay line 15
Figure2.11 The block diagram of previous circuit[3] 17
Figure 2.12 Frequency response of both transfer function: (a) the modified bilinear (b) the transfer function of the previous circuit 18
Figure 3.1 The block diagram of the second order integral bandpass filter 19
Figure 3.2 The block of integrator 20
Figure 3.3 Comparison of frequency warping effects: 1. Ideal 2. LDI 3. Bilinear 4. Modified Bilinear 21
Figure 3.4 The block diagram of equation 3.10 23
Figure 3.5 the schema of nonoverlapping two phase clock 23
Figure 3.6 Graph of (a)the block of input (b)the non-overlap clock (c)the table of summing node 24
Figure 3.7 The input circuit 24
Figure 3.8 Graph of (a)the block of output end (b)the non-overlap clock (c)the table of summing node 25
Figure 3.9 The output circuit 25
Figure 3.10 The simple modified bilinear integrator 26
Figure 3.11 Dummy switch technique 27
Figure 3.12 The grounded-gate technique:(a) The SI memory cell with grounded-gate feedback[8] (b) A simplified grounded-gate SI integrator[9] 28
Figure 3.13 The complete Modified bilinear integrator 29
Figure 3.14 The block of current amplifier 30
Figure 3.15 The circuit of current amplifier 30
Figure 3.16 A scheme of transfer function of filter 31
Figure 3.17 A scheme of transfer function of lowpass filter 32
Figure 3.18 A scheme of second order bandpass filter 33
Figure 3.19 The schematic diagram of whole filter circuit 35
Figure 4.1 The block of the non-over lapping clock generator 37
Figure 4.2 The schematic of the non-over lapping clock generator 37
Figure 4.3 The schematic of the modified bilinear integrator 38
Figure 4.4 The schematic of the proposed bilinear second order integral filter 38
Figure 4.5 The Hspice simulation result of the bilinear second order integral filter in central frequency 40
Figure 4.6 Frequency response of our circuit : (a) s-domain transfer function (b) z-domain transfer function (c) Hspice simulation result is present by star symbol 40
Figure 4.7 The layout of the modified bilinear integrator and the non-over lapping clock generator 41
Figure 4.8 The layout of the modified bilinear integrator(including pads) 41
Figure 4.9 The proposed modified bilinear integrator’s measurement circuit 42
Figure 4.10 The result of the modified bilinear integrator in central frequency (pre-simulation) 43
Figure 4.11 The result of the modified bilinear integrator (post-simulation) : (a) Input signal (b) Output signal 44
Figure 4.12 The simulation of warping effect:(a) Ideal (b) Matlab simulation (c) Hspice pre-simulation (d) measurement result is present by star symbol 44


Table 4.1 The component values of the bilinear second order integral filter 39
Table 4.2 The simulation and measurement results of time response 45
Table 4.3 Comparison with original structure 45
參考文獻 References
Reference

[1] S. M. Faruque and B. B. Bhattacharyya, “A Modified Bilinear Integrator”, Proceedings of the IEEE ISCAS, pp. 736-737, 1989.

[2] S. M. Faruque and B. B. Bhattacharyya, “Synthesis of digital filters by means of a Modified Bilinear Transformation”, Proceedings of the IEEE ISCAS, pp. 640-641, 1990.

[3] Shen-Luan Liu, Chih-Hsien Chen, Hen-Wai Tsao and Jingshown Wu, “A Switched-Current Modified Bilinear Integrator and Its Applications”, Proceedings of the IEEE ISCAS, pp. 1805-1808, 1991.

[4] Psychalinos, C., Goutis, C.E., “Improved switched-current (SI) bilinear integrator circuit”, Electronics Letters Volume: 31, Publication Year: 1995 , Page(s): 26 – 27

[5] Psychalinos, C., “Switched-current bilinear integrator realised using one current mirror”, Electronics Letters Volume: 37, Publication Year: 2001 , Page(s): 1210 –1211

[6] Hughes, J.B., Moulding, K.W., “A Switched-Current Double Sampling Bilinear Z-Transform Filter Technique”, Vol. : 5 Publication Year: 1994, Page(s): 293 – 296

[7] Hong-Kui Yang, El-Masry, E.I., “A Novel Double Sampling Technique for Delta Sigma Modulators”, Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on Publication Year: 1994, Page(s): 1187 - 1190 vol.2
[8] Hughes, J.B., Moulding, K.W., “Switched-current signal processing for video frequencies and beyond”, Solid-State Circuits, IEEE Journal of Volume: 28, Issue: 3
Publication Year: 1993 , Page(s): 314 – 322

[9] Georgantas, T., Bouras, S., Panananos, Y. Dervenis, D., “SWITCHED-CURRENT ΣΔ MODULATOR FOR BASEBAND CHANNEL APPLICATIONS”, Circuits and Systems, 2000. IEEE ISCAS Publication Year: 2000, Page(s): 413 - 416 vol.4

[10] Balachandran, G.K., Allen, P.E., “Switched-Current Circuits in Digital CMOS Technology With Low Charge-Injection Errors”, lid-State Circuits, IEEE Journal of
Volume: 37 , Issue: 10, Publication Year: 2002 , Page(s): 1271 - 1281
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