在3GPP-LTE通訊系統的標準中，為了面對外在環境狀況的變化，定義了許多不同長度的快速傅立葉轉換點數，然而以往只支援單一種運算點數的硬體架構已無法滿足現今的需求，因此我們設計一套獨立且高效能的硬體架構，充分運用可重置式的設計概念，進而支援3GPP-LTE通訊系統中4至4096點等48種運算點數，使整體系統更符合需求與實用性。
本系統在主要硬體架構上發展出3項重要技術：(1) 組合基底式運算單元：以單一路徑延遲回授架構下的Radix-5^2運算為設計基礎，並充分運用可重置式與硬體重複使用的概念，在不增加額外運算元件(例如加法器與乘法器)的前提之下，設計出能支援18種基底的運算架構。(2) 高效能先進先出暫存器管理規劃方法：面對48種不同長度的運算點數，透過此技術來妥善規劃儲存單元的配置，並設計出可切換之先進先出暫存器，使硬體的使用率發揮到最大。(3) 雙階段角度近似之旋轉因子產生器：面對多種運算點數的情況下，此技術能夠產生系統所需的旋轉因子，並且有效地降低硬體成本，進一步符合行動通訊系統的需求。
在晶片實現上，利用TSMC-40nm CMOS 製程技術，晶片的核心面積只有0.415 mm^2，操作頻率可達到526.32 MHz，而系統最高的總功耗為42.76 mW。相較於目前文獻上的其它架構，我們支援最多種類的運算點數，並且擁有最高操作頻率、低面積與低功耗等效能表現，提供學界和業界一個強而有力的設計方法。

In 3GPP-LTE communication standard, it defines many Fast Fourier Transform(FFT) points for accommodating different outside environments. However, it is not enough to satisfy current demands for the traditional design which only supports single mode FFT points. Therefore, we design a high-performance FFT hardware architecture which makes good use of reconfigurable concept. It can support 48 modes which perform 4 to 4096 FFT points and can be suitable for 3GPP-LTE communication standard.
In our proposed system, we develop three design techniques. (1) Combined-radix Processing Element(CR-PE)：We utilize the reconfigurable concept and hardware reuse property in radix-5^2 base. Without extra primary hardware resource (adders or multipliers), it can execute 18 radix-type of FFT processing. (2) Efficient First-in First-out Management Scheme(EFMS)：By this technique, we design the Switchable First-in First-out(S-FIFO) for facing with 48 modes of FFT points. The FIFO plan is well-managed and suitably located to maximize the storage hardware usage. (3) Two-level Angle-approximation Rotation(TAAR)：This technique is not only able to generate the twiddle factors needed by the system, but also reduce hardware costs efficiently. It further satisfies the requirement of mobile communication system.
In the chip implementation, the core area is only 0.415 mm^2 by using TSMC 40-nm CMOS technology. The operating frequency can achieve 526.32 MHz and the maximum power dissipation is 42.76 mW. As compared with other state-of-the-art works, our design has the highest working frequency and supports most FFT points. This design methodology provides a powerful FFT design scheme for both academic and industrial fields.

論文審定書 i
誌謝 ii
摘要 iii
Abstract iv
目錄 v
圖次 vi
表次 ix
第一章 緒論 1
1.1 背景 1
1.2 動機與設計目標 1
1.3 論文架構 3
第二章 傅立葉轉換介紹 4
2.1 離散傅立葉轉換與反離散傅立葉轉換 4
2.2 快速傅立葉轉換 5
2.3 單一路徑延遲回授架構 7
2.3.1 Radix-2、Radix-4與Radix-8的演算法與架構 7
2.3.2 Radix-3的演算法與架構 10
2.3.3 Radix-5的演算法與架構 11
2.3.4 Radix-22與Radix-23的演算法與架構 12
第三章 新提出的組合基底演算法推導與分析 14
3.1 組合基底演算法介紹 14
3.2 組合基底之優勢分析 17
第四章 新提出的可重置式硬體架構 18
4.1 系統簡介 18
4.1.1 適用於3GPP-LTE通訊系統之可重置式想法與實現 18
4.1.2 主架構介紹 20
4.2 技術一：組合基底式運算單元 22
4.2.1 技術介紹 22
4.2.2 電路架構 26
4.2.3 效能分析 28
4.3 技術二：高效能先進先出暫存器管理規劃方法 32
4.3.1 問題陳述 32
4.3.2 技術架構與應用 32
4.4 技術三：雙階段角度近似之旋轉因子產生器 37
4.4.1 設計想法 37
4.4.2 硬體架構 39
4.4.3 效能分析 42
4.4.4 硬體實現結果 47
第五章 晶片實現 48
5.1 合成結果分析 49
5.2 晶片可測試性設計結果 50
5.3 自動測試圖樣產生系統之結果 51
5.4 系統晶片佈局成果 52
5.5 效能比較 53
第六章 結論與未來展望 56
6.1 結論 56
6.2 未來展望 56
參考文獻 57

[1] S. He and M. Torkelson, "A new approach to pipeline FFT processor," in Parallel Processing Symposium, 1996., Proceedings of IPPS'96, The 10th International, Apr. 1996, pp. 766-770.
[2] K. George and C.-I. H. Chen, "Configurable and expandable FFT processor for wideband communication," in Instrumentation and Measurement Technology Conference Proceedings, 2007. IMTC 2007. IEEE, May 2007, pp. 1-6.
[3] D. Hiremath and B. Rajeshwari, "Implementation of Pipelined Radix-2 FFT using SDC and SDF architecture," in Region 10 Conference (TENCON), 2016 IEEE, Nov. 2016, pp. 1660-1663.
[4] I. A. Qureshi and F. Qureshi, "Generalized twiddle factor index mapping of radix-2 fast Fourier transform algorithm," in Software Engineering and Service Science (ICSESS), 2014 5th IEEE International Conference on, Jun. 2014, pp. 381-384.
[5] Z. Qian and M. Margala, "Low-power split-radix FFT processors using radix-2 butterfly units," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, pp. 3008-3012, Sep. 2016.
[6] M. Hasan, T. Arslan, and J. S. Thompson, "A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications," IEEE Transactions on Consumer Electronics, vol. 49, pp. 128-134, Feb. 2003.
[7] M. Garrido, M. Á. Sánchez, M. L. López-Vallejo, and J. Grajal, "A 4096-point radix-4 memory-based FFT using DSP slices," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, pp. 375-379, Jan. 2017.
[8] Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, "A dynamic scaling FFT processor for DVB-T applications," IEEE Journal of solid-state circuits, vol. 39, pp. 2005-2013, Nov. 2004.
[9] E. Dubois and A. Venetsanopoulos, "A new algorithm for the radix-3 FFT," IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 26, pp. 222-225, Jun. 1978.
[10] S. K. Bashar, "An efficient approach to the computation of fast fourier transform (FFT) by Radix-3 algorithm," in Informatics, Electronics & Vision (ICIEV), 2013 International Conference on, May 2013, pp. 1-5.
[11] J. Löfgren and P. Nilsson, "On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems," in NORCHIP, 2011, Nov. 2011, pp. 1-4.
[12] A. Karlsson, J. Sohl, and D. Liu, "Cost-efficient mapping of 3-and 5-point DFTs to general baseband processors," in Digital Signal Processing (DSP), 2015 IEEE International Conference on, Jul. 2015, pp. 780-784.
[13] T. Patyk, F. Qureshi, and J. Takala, "Hardware-Efficient Twiddle Factor Generator for Mixed Radix-2/3/4/5 FFTs," in Signal Processing Systems (SiPS), 2016 IEEE International Workshop on, Oct. 2016, pp. 201-206.
[14] S. He and M. Torkelson, "Designing pipeline FFT processor for OFDM (de) modulation," in Signals, Systems, and Electronics, 1998. ISSSE 98. 1998 URSI International Symposium on, Oct. 1998, pp. 257-262.
[15] G. Bi and G. Li, "Pipelined structure based on radix-2^2 FFT algorithm," in Industrial Electronics and Applications (ICIEA), 2011 6th IEEE Conference on, Jun. 2011, pp. 2530-2533.
[16] N. H. Cuong, N. T. Lam, and N. D. Minh, "Multiplier-less based architecture for variable-length FFT hardware implementation," in Communications and Electronics (ICCE), 2012 Fourth International Conference on, Aug. 2012, pp. 489-494.
[17] Y. Chen, Y.-C. Tsao, Y.-W. Lin, C.-H. Lin, and C.-Y. Lee, "An indexed-scaling pipelined FFT processor for OFDM-based WPAN applications," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, pp. 146-150, Feb. 2008.
[18] D.-s. Kim and S.-y. Lee, "Dual input radix 2^3 SDF IFFT/FFT processor for wireless multi-channel real sound speakers using time division duplex scheme," IEEE Transactions on Consumer Electronics, vol. 55, Nov. 2009.
[19] Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, "A 1-gs/s fft/ifft processor for uwb applications," IEEE Journal of solid-state circuits, vol. 40, pp. 1726-1735, Aug. 2005.
[20] http://www.3gpp.org/technologies/keywords-acronyms/98-lte.
[21] T.-D. Chiueh and P.-Y. Tsai, OFDM baseband receiver design for wireless communications: John Wiley & Sons, Apr. 2008.
[22] C. Yu and M.-H. Yen, "Area-efficient 128-to 2048/1536-point pipeline FFT processor for LTE and mobile WiMAX systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, pp. 1793-1800, Sep. 2015.
[23] G. Wang, B. Yin, I. Cho, J. R. Cavallaro, S. Bhattacharyya, and J. Takala, "Efficient architecture mapping of FFT/IFFT for cognitive radio networks," in Acoustics, Speech and Signal Processing (ICASSP), 2014 IEEE International Conference on, May 2014, pp. 3933-3937.
[24] J. W. Cooley and J. W. Tukey, "An algorithm for the machine calculation of complex Fourier series," Mathematics of computation, vol. 19, pp. 297-301, Apr. 1965.
[25] K.-J. Yang, S.-H. Tsai, and G. C. Chuang, "MDC FFT/IFFT processor with variable length for MIMO-OFDM systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, pp. 720-731, Apr. 2013.
[26] M. Wang and Z. Li, "A hybrid SDC/SDF architecture for area and power minimization of floating-point FFT computations," in Circuits and Systems (ISCAS), 2016 IEEE International Symposium on, May 2016, pp. 2170-2173.
[27] C.-H. Yang, T.-H. Yu, and D. Markovic, "Power and area minimization of reconfigurable FFT processors: A 3GPP-LTE example," IEEE journal of solid-state circuits, vol. 47, pp. 757-768, Mar. 2012.
[28] J. Chen, J. Hu, S. Lee, and G. E. Sobelman, "Hardware efficient mixed radix-25/16/9 FFT for LTE systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, pp. 221-229, Feb. 2015.
[29] K.-F. Xia, B. Wu, T. Xiong, and T.-C. Ye, "A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, pp. 1919-1929, Jun. 2017.
[30] X.-Y. Shih, Y.-Q. Liu, and H.-R. Chou, "48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, pp. 1456-1467, Jun. 2017.