本論文包含適用於生醫晶片系統設計之兩個主題：具製程及溫度補償振盪器，以及連續逐次逼近式類比數位轉換器。
第一個主題提出一具製程及溫度補償振盪器，可應用於植入式脊椎電刺激系統。本設計以差動環形振盪器為主要架構，搭配一具製程及溫度補償之補償電路，依照製程或環境溫度的改變，其輸出之補償電壓將回授給予差動環形振盪器，使振盪器產生一不隨製程及溫度改變之時脈頻率，並以電晶體及電阻代替常見的BJT作為抗溫度飄移元件，有效縮小面積，並使頻率飄移量於溫度0 ~ 100 °C間，可達到小於3.07 %。整體電路以TSMC 0.25 μm 60V HV Mixed-Signal 1P3M Polycide CMOS製程實現，並以實際量測來佐證本設計之正確性。
第二個主題提出一連續逐次逼近式類比數位轉換器，可應用於FPW過敏原感測系統。以一對取樣電容對輸入電壓取樣，再將此電壓輸入比較器進行比較，其結果輸出至開關控制邏輯進行判斷並輸出對應控制訊號，電容陣列之各位元電容將對應該控制訊號對取樣電容進行充電或放電。其中電容陣列架構採用電荷分享式架構，並將電容陣列分為兩段式(Split array)以求減少MSB之電容值，進而使整體電路面積縮小。整體電路以TSMC 0.18 μm Mixed-Signal 1P6M Polycide CMOS製程實現。

This thesis consists of two topics, i.e., a process and temperature compensation oscillator and a successive-approximation register analog to digital converter, which are mainly designed for biomedical system applications.
The first topic presents a process and temperature compensation oscillator for an implantable spinal cord stimulation system. This design is basically a ring-based oscillator, particularly including a temperature and process compensation circuit to provide a compensation bias voltage to stabilize the frequency such that the variations of the temperature and process can be reduced. To reduce the chip size, we use transistors and resistors to replace the conventional BJT as the temperature compensation component. The frequency variation verified on silicon is less than 3.07 % in the temperature range from 0 to 100 °C. This design is realized using TSMC 0.25 μm 60V HV BCD CMOS technology.
The second topic presents a successive-approximation register analog to digital converter (SAR ADC) for FPW-based antibody sensing systems. The input voltages are sampled by the sampling capacitors and compared by a comparator. Then, the comparison result will be transmitted to the following switch control logic. The capacitors in the array will charge or discharge the sampling capacitors based on the control signal generated by the switch control logic. The capacitor array is based on a charge sharing architecture, where a split capacitor array is used to reduce the size of the MSB capacitor. The proposed design is realized using TSMC 0.18 μm CMOS technology.

摘要 i
Abstract ii
圖次 v
表次 viii
第一章 概論 1
1.1 前言 1
1.2 相關文獻與研究討論 3
1.2.1 具補償功能之振盪器 3
1.2.2 連續逐次逼近式類比數位轉換器 6
1.3 研究動機 10
1.4 論文大綱 10
第二章 具製程及溫度補償振盪器 11
2.1 簡介 11
2.2 具製程及溫度補償振盪器 11
2.3 具製程及溫度補償振盪器電路設計 12
2.3.1 差動環形振盪器 12
2.3.2 複製電路 14
2.3.3 製程溫度補償電路 15
2.3.4 電壓穩壓器 19
2.3.5 雙端單端轉換電路 21
2.4 電路模擬與預計規格 22
2.4.1 補償效果模擬分析 22
2.4.2 未補償模擬分析 26
2.4.3 預計規格與效能比較 27
2.5 晶片佈局 29
2.6 晶片實作與測量結果 31
2.6.1 晶片量測結果與分析 32
2.6.2 預計規格與實測結果 34
2.7 結果與討論 35
第三章 連續逐次逼近式類比數位轉換器電路架構 36
3.1 簡介 36
3.2 連續逐次逼近式類比數位轉換器電路架構 36
3.3 連續逐次逼近式類比數位轉換器電路設計 40
3.3.1 電荷分享電容陣列 40
3.3.2 靴帶式取樣開關 43
3.3.3 動態電壓比較器 45
3.3.4 非同步控制邏輯產生電路 47
3.3.5 開關控制邏輯電路 48
3.4 電路模擬及預計規格 50
3.4.1 非同步控制邏輯功能驗證 50
3.4.2 開關控制邏輯功能驗證 51
3.4.3 SAR_ADC功能驗證 52
3.5 晶片佈局 54
3.6 結果與討論 55
第四章 結論與未來工作 56
參考文獻 59

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