近年來，多媒體應用被廣泛地使用在許多嵌入式以及可攜式系統中，例如行動電話、MP3播放器以及個人數位助理，這些產品在高效能的限制下都需要較低的功率消耗。因此，有效的低功率設計變成了超大型積體電路設計中一個極為重要的研究主題。此外，乘法單元總是位於多媒體系統電路的臨界路徑(critical path)上，而且對數位電子產品的效能以及功率消耗具有決定性的影響力。為了達到高效能以及延長電池的可用時數，發展一個高效能且低功率的乘法器是非常重要的。
在多媒體和數位訊號處理系統中，許多低功率技術藉由關閉不必要的運算電路來減少乘法器的功率消耗。而且，這些系統中的乘法運算通常允許資料在輸出精確度上具有些許失真，以便節省更多的功率消耗。基於這些概念，本論文根據不同多媒體和數位訊號處理系統中輸入資料特性以及乘法算術特色，提出新的功率縮減和截斷技術以幫助我們設計節能乘法器及高精確度固定寬度乘法器。
在陣列及樹狀乘法器的設計方面，我們首先提出一個低功率管線化固定寬度乘法器，它能夠動態地依據輸入資料範圍的大小來關閉不需要運算的加法元件。此外，它還提供了功率消耗和輸出精確度之間的彈性折衷，可重置的特色對於有不同精確度需求的系統而言是非常有用的。其次，我們提出一個低功率可重置布斯乘法器，它提供多種乘法運算模式並且盡可能地消除乘法器中多餘的符號運算。對於同時要求運算效能和彈性的系統而言，此乘法器能夠有效地減少其功率消耗。雖然這兩種低功率乘法器能獲得可觀的功率節省，但在錯誤補償電路的複雜度及平均誤差和均方誤差效能方面上仍不適用於含有大量乘累加運算的多媒體系統。為了有效地改善精確度及電路複雜度，我們針對固定寬度樹狀乘法器和固定寬度改良式布斯乘法器提出了新的錯誤補償電路。
在浮點乘法器設計方面，我們提出一個低功率可變潛伏期浮點乘法器，它符合電機電子工程學會二進位浮點數算術標準 (IEEE 754) 並且適用於三維圖學及多媒體應用。在此架構中，我們首先將有效數乘法器分割成上、下兩半部。其次，針對進位位元、黏著位元和上半部有效數乘積提出一項有效的預測機制。當預測正確時，關閉有效數乘法器的下半部運算，因此浮點乘法運算能消耗更少功率並且提早完成。
在模數乘法器設計方面，為了設計出高效能及低功率之模數乘法器，我們提出一個有效的模數乘法演算法。它利用商數管線化及消除非必要運算的技術，移除基底2之模數乘法演算法中資料相依性和多餘的計算週期，以便有效改善模數乘法器中的運算速度、功率消耗及能量消耗。

Recently, multimedia applications are used widely in many embedded and portable systems, such as mobile phones, MP3 player and PDA, which require lower power consumption within high performance constraints. Therefore, power-efficient design becomes a more important objective in Very Large Scale Integration (VLSI) designs. Moreover, the multiplication unit always lies on the critical path and ultimately determines the performance and power consumption of arithmetic computing systems. To achieve high-performance and lengthen the battery lifetime, it is crucial to develop a multiplier with high-speed and low power consumption.
In multimedia and digital signal processing (DSP) applications, many low-power approaches have been presented to lessen the power consumption of multipliers by eliminating spurious computations. Moreover, the multiplication operations adopted in these systems usually allow accuracy loss to output data so as to achieve more power savings. Based on these conceptions, this dissertation considers input data characteristics and the arithmetic features of multiplications in various multimedia and DSP applications and presents novel power reduction and truncation techniques to design power-efficient multipliers and high-accuracy fixed-width multipliers.
In the design of array and tree multipliers, we first propose a low power pipelined truncated multiplier which dynamically deactivates non-effective circuitry based on input range. Moreover, the proposed multiplier offers a flexible tradeoff between power reduction and product precision. This reconfigurable characteristic is very useful to systems which have different requirement on output precision. Second, a low-power configurable Booth multiplier that supports several multiplication modes and eliminates the redundant computations of sign bits in multipliers as much as possible is developed. This architecture can efficaciously decrease the power consumption of systems which demand computing performance and flexibility simultaneously. Although these two kinds of low power multipliers can achieve significant power savings, the hardware complexity of error compensation circuits and error performance in terms of the mean error and mean-square error are unsuitable for many multimedia systems composed of a large amount of multiply-accumulate operations. To efficiently improve the accuracy with less hardware complexity, we propose new error compensation circuits for fixed-width tree multipliers and fixed-width modified Booth multipliers.
In the design of floating-point multipliers, we propose a low power variable-latency floating-point multiplier which is compliant with IEEE 754-1985 and suitable for 3-D graphics and multimedia applications. In the architecture, the significand multiplier is first partitioned into the upper and lower parts. Next, an efficient prediction scheme for the carry bit, sticky bit, and the upper part of significand product is developed. While the correct prediction occurs, the computation of lower part of significand multiplier is shut down and therefore the floating-point multiplication can consume less power and be completed early.
In the design of modular multipliers, we propose an efficient modular multiplication algorithm to devise a high performance and low power modular multiplier. The proposed algorithm adopts the quotient pipelining and superfluous-operation elimination technique to discard the data dependency and redundant computational cycles of radix-2 Montgomery’s multiplication algorithm so that the operation speed, power dissipation, and energy consumption of modular multipliers can be significantly improved.

Chapter 1 INTRODUCTION 1
1.1 Power-Efficient Pipelined Truncated Multipliers withVarious Precision 3
1.2 Power-Efficient Configurable Booth Multiplier 4
1.3 High-accuracy Low-cost Compensation Circuits for Signed Tree-based Fixed-width Multipliers 5
1.4 High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications 6
1.5 Variable-Latency Floating-Point Multipliers for Low-Power Applications 7
1.6 High-Performance and Low-Power Montgomery Multiplication for RSA Cryptosystems 8
1.7 Organization of the Dissertation 9
Chapter 2 POWER-EFFICIENT PIPELINED TRUNCATED MULTIPLIERS WITH
VARIOUS PRECISION 10
2.1 Introduction 10
2.2 Problem Description 13
2.3 Low-power Multiplier with Various Precision 16
2.3.1 Basic Dynamic-range Detector 19
2.3.2 Modified Dynamic-range Detector 22
2.3.3 Sign-bit Generator and Sign-extension Unit 26
2.4 Experimental Results 28
2.5 Conclusion 38
Chapter 3 DESIGN OF POWER-EFFICIENT CONFIGURABLE BOOTH MULTIPLIER 39
3.1 Introduction 39
3.2 Configurable Multiplication with One-level Recursion 43
3.3 Power-Aware Configurable Booth Multiplier 50
3.3.1 Dynamic Range Detector 52
3.3.1.1 Switching logic 54
3.3.1.2 Shutdown logic 56
3.3.2 Error-compensation Circuit 60
3.3.3 EV generator and CV generator 62
3.3.4 Adjustor 67
3.3.5 Sign-bit Generator and Sign-extension Unit 68
3.3.6 Error Analysis 70
3.4 Experimental Results 72
3.5 Conclusion 79
Chapter 4 HIGH-ACCURACY LOW-COST COMPENSATION CIRCUITS FOR SIGNED TREE-BASED FIXED-WIDTH MULTIPLIERS 80
4.1 Introduction 80
4.2 Background and Motivation 82
4.3 Proposed Low-cost Compensation Circuits 90
4.4 Experimental Results 98
4.5 Conclusion 103
Chapter 5 HIGH-ACCURACY FIXED-WIDTH MODIFIED BOOTH MULTIPLIERS FOR LOSSY APPLICATIONS 104
5.1 Introduction 104
5.2 Fundamental of Modified Booth Multiplier 108
5.3 Proposed Fixed-width Modified Booth Multiplier 111
5.3.1 Proposed Error Compensation Function 112
5.3.2 Proposed Low Error Compensation Circuit 122
5.3.3 Error Performance 127
5.4 Experimental Results 131
5.5 Conclusion 135
Chapter 6 VARIABLE-LANTECY FLOATING-POINT MULTIPLIERS FOR LOW-POWER APPLICATIONS 137
6.1 Introduction 137
6.2 Low-power Floating-point Multiplication 139
6.2.1 Prediction of c0, r, and s 141
6.2.2 Proposed Algorithm 145
6.3 Architecture and Implementation 149
6.4 Conclusion 154
Chapter 7 DESIGN OF HIGH-PERFORMANCE AND LOW-POWER MONTGOMERY MODULAR MULTIPLIER FOR RSA CRPTOSYSTEMS 155
7.1 Introduction 155
7.2 Montgomery’s Modular Multiplication Algorithm 158
7.3 Proposed Montgomery Modular Multiplication Algorithm 161
7.3.1 Quotient Pipelining 162
7.3.2 Superfluous Operation Elimination 166
7.3.3 Proposed Modified Modular Multiplication Algorithm 169
7.4 Architecture of Modified Modular Multiplier 172
7.4.1 Barrel Register Full Adder Component 172
7.4.2 Proposed Modular Multiplication Architecture 173
7.5 Experimental Results 176
7.6 Conclusion 177
Chapter 8 CONCLUSION AND FUTURE WORK 178
8.1 Conclusion 178
8.2 Future Work 181
References 182
Publication Lists 195

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