積體電路製程90奈米已經開始量產，可是晶粒凸塊間距量產只有180微米，主因是基板焊墊錫鉛刮印製程180微米之良率低於80%，而且150微米以下間距之良率低於50%。
基版銲墊上需覆蓋一錫鉛層，經過高溫迴銲爐時會與晶粒上的錫鉛凸塊熔接，而目前基版銲墊上之錫鉛層是經由印刷方式將錫膏刮印在基版上，印刷方式的產能高而且成本低，但150微米以下間距之良率太低無法符合量產成本，所以基版廠商改以電鍍方式將基版銲墊間距縮小到100微米以下，但當間距縮小時凸塊的體積也相對縮小，當錫鉛凸塊縮小後其結構可能無法承受可靠度測試，所以此一改變封裝製程需面對如何將晶粒上錫鉛凸塊與基版上的銅凸塊結合的難題，此即為本論文研究的重點。
在本論文先以數值分析軟體模擬比較覆晶封裝產品使用錫鉛金屬凸塊與銅金屬凸塊基板抵抗疲勞變形的能力，再比較基板使用錫鉛金屬凸塊與銅金屬凸塊之外觀品質特性，最後是驗證覆晶封裝製程的可行性與可靠度測試。
本論文的研究結果不但證實了覆晶封裝產品可以使用銅金屬凸塊基板，而且覆晶封裝製程可以不用變更任何參數與及機台之機構，顯示量產完全沒有問題。
關鍵字：覆晶封裝產品、基板、凸塊、冷焊、脫層

90nm wafer process has been released in production, but the bump pitch released in production is 180um. The major problem is the yield of solder paste printing process below 180um will be less than 80%. It means the cost will be very high. Thus it is difficult to make 150um bump pitch by using printing process in production.
Substrate C4 pad will be bumped by pre-solder, and it will be jointed with wafer bump after re-flow process. The printing process is the most popular process in C4 pad pre-solder due to low cost and high throughput. But the challenge of 150um and even more of the wafer bump pitch shrinkage are the inevitable trend. So, a lot of substrate manufacturers are trying to develop the new process for C4 pro-solder pitch less than 100um.
As soon as the C4 pad pre-solder pitch has been shrunk, the solder volume will be shrunk as well. It means the bump structure will be getting weak, and it may not pass the reliability tests. Thus, to evaluate the workability of bump structure is our purpose.
First, the simulation software is used to compare the fatigue lives of two structures by using solder bump and copper bump substrates during thermal cycling test, and then to proceed the whole FCBGA process and reliability tests.
The result of evaluation confirm the workability of FCBGA product using copper bump substrate, and it can be used with the same parameter and machine in solder bump substrate.

Keyword：FCBGA, Substrate, Bump, Cold Joint, Delamination

誌謝 I
目錄 II
表目錄 III
圖目錄 IV
摘要 VI
Abstract VII
第一章 序論 1
1.1前言 1
1.2文獻回顧 2
1.3覆晶封裝產品使用的基板 5
1.3.1基層式2+2+2六層板的結構 5
1.3.2基板金屬凸塊印刷及電鍍製程的比較 5
1.3.3印刷製程與電鍍製程金屬凸塊之比較 8
1.4覆晶封裝製程之簡介 9
1.4.1製程流程 9
1.4.2上晶粒製程 10
1.4.3高溫熔接製程 10
1.5可靠度測試 11
第二章 數值分析模擬 14
2.1數值分析 14
2.2分析結果 15
2.2.1變形量 15
2.2.2金屬凸塊潛在破壞性之分析 15
第三章 實驗工作 18
3.1實驗規劃 18
3.2測試樣品介紹 18
3.3實驗流程 19
3.3.1銅金屬凸塊基層式2+2+2六層板 19
3.3.2覆晶封裝產品製程 20
3.3.3可靠度測試 23
第四章 實驗結果 25
4.1銅金屬凸塊基層式2+2+2六層板測試結果 25
4.2上晶粒製程測試結果 26
4.3可靠度測試結果 26
第五章 討論 28
第六章 結論 32
參考文獻 70

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