Responsive image
博碩士論文 etd-0207107-141151 詳細資訊
Title page for etd-0207107-141151
論文名稱
Title
先進疊層晶片封裝的銲線佈局研究
Study of the advanced bonding layout of stack chip assembly
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
50
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2006-12-29
繳交日期
Date of Submission
2007-02-07
關鍵字
Keywords
銲線佈局、晶片封裝
bonding layout, chip assembly
統計
Statistics
本論文已被瀏覽 5797 次,被下載 17
The thesis/dissertation has been browsed 5797 times, has been downloaded 17 times.
中文摘要
電子產品功能越來越強大, 在本論文中提出一個創新的接線佈局方法來取代現有的又高又長的多層接線封裝; 現今的HSBGA(Heat Slug Ball Grid Array散熱片型球閘列封裝)的接線佈局設計, 為了滿足越來越多層化的晶片銲墊接口設計, 接線的複雜度也大為增加, 導致接線又高又長, 除了材料費用增加, 接線間的開短路良率損失也增加, 並且造成作業程序的困難度增高, 進而增加了製造成本.
本論文的“先進疊層晶片封裝的銲線佈局研究”, 改善了接線的設計以及應用在雙層晶片的散熱片型球閘列封裝中, 這個設計因為較短的接線線長而改善了元件的電性特性, 及因為在工作晶片與散熱片間增加了一塊散熱用晶片而擁有較好的散熱特性.
研究分為電性表現模擬(軟體: HF99 v9.0)、散熱表現模擬(軟體: commercial code ANSYS)及模擬實際生產時的產品佈線繪圖(AutoCAD)以及實驗的打線線弧參數的調整(機型及軟體: K&S 8028 Maxum), 並進行SEM分析來確認結果.
依據分析模擬結果,“先進疊層晶片封裝的銲線佈局研究”有三個優點: 降低 40% 熱阻 qJC, 電壓輸出入損失改善了30~40%, 以及因為減短了接線線長由4.5mm到3mm, 節省了1/3 金線材料消耗, 也就是減少了6%的封裝成本.
Abstract
Modern development of electronic devices requires the integration of more and more powerful functions within the same amount of space. However, this is accompanied by increased difficulties within the manufacturing and packaging processes. A proposal for the arrangement of wire connecting is suggested. In this work, which is to replace the multi-tier design with conventional high & long wire bonding. The advance of bonding layout of the stack die HSBGA (Heat Slug Ball Grid Array) chip assembly can enhance wire bonding with electrical performance by shortening wire length. This promises a better thermal performance of thermal consumption between the function die and heat slugs.
This analysis includes simulations of electrical and thermal performance, as well as simulations of drawing layout for an actual production, the bonding looping parameters optimization, and SEM analysis to confirm the results.
Based on the above analyses, the results reveal three advantages of the proposal of “Advance bonding layout of chip assembly” which are:
(1)reduction of 40% thermal resistance,
(2)θJC voltage insertion loss improvement of 30~40%, and
(3)reduction of the gold wire length from 4.5mm to 3mm, saving 1/3 of gold wire consumption. Overall, assembly costs can be reduced by 6%.
目次 Table of Contents
中文摘要……………………………………………………………I /2 Abstract………………………………………………………………II /3
Contents……………………………………………………………III /5 Chapter 1. Introduction………………………………………………10
Chapter 2. New package layout proposal……………………………..21 Chapter 3. Experiment ………………………………………………..25 3-1 Material preparation…………………………………………….23 3-2 Thermal performance Simulation……………………………….29
3-3 Electrical performance Simulation………………………………35
Chapter 4. Results and Discussions…………………………………...37 4-1 Electrical and thermal performance………………………………37 4-2 Package assembly price cost down performance……….…………43 Chapter 5. Summary…………………………………………………45 Reference……………………………………………………………..46
參考文獻 References
Reference
1. T. Aoki, W. Sauter, and T. Hisada, “Manufacturability and Reliability of Fine Pitch Wire bonding”, (2004 Electronic Components and Technology Conference ), 2004, page 2-3.
2. Y. F. Yao, Z. P. Xiong, X. Gu and K. H. Chua , “Assembly Process Development of 50um Fine Pitch Wire Bonded Devices”, (2004 Electronic Components and Technology Conference ) , 2004, page 3.
3. 張千惠,“Mold-Flow Analysis of High-Density IC Encapsulation”, 私 立 中 原 大 學 機械工程學系 碩士論文, 2002, page 36-37.
4. E. Awad, H. Ding, R. S. Graf, and J.J. Maloney ,“Stacked-Chip Packaging: Electrical, Mechanical, and Thermal Challenges”, IBM Microelectronics, 2004 Electronic Components and Technology Conference, 2004, page 6 .
5. W. Sauter, T. Aoki, T. Hisada, F. Beaulieu, S. Allard, K. Ostrowski,“Manufacturability and Reliability of Different Size Wirebonds on different Al Pad Structures”, 2004 Electronic Components and Technology Conference, 2004, page 2-4.


6. C. W. Tan, Y. C. Chan,“Reliability and Thermo-Mechanical Properties of Gold Ribbon Wire Bonding”, 2004 Electronic Components and Technology Conference, 2004, page 4-6.
7. Y. Liu, S. Irving and T. Luk,“Thermosonic Wire Bonding Process Simulation and Bond Pad Over Active Stress Analysis”, 2004 Electronic Components and Technology Conference, 2004, page 7-8.
8. J. Y. Chuang, S. P. Tseng, and J. A. Yeh,“Radio Frequency Characterization of Bonding Wire Interconnections in a Molded Chip”, Taiwan, 2004 Electronic Components and Technology Conference, , 2004, page 2-3.
9. K. Takahashi, Y. Taguchi, M. Tomisaka, H. Yonemura, M. Hoshino, M. Ueno, Y. Egawa, Y. Nemoto, Y. Yamaji, H. Terao, M. Umemoto, K. Kameyama, A. Suzuki, Y. Okayama, T. Yonezawa, K. K. Tsukuba,“Process Integration of 3D Chip Stack with Vertical Interconnection”, 2004 Electronic Components and Technology Conference, 2004, page 1-2.
10. D. Draper, R. Kollipara, M. Li,“High-Performance, Four-layer, Wire-Bonded, Plastic Ball Grid Array Package for 10 Gbps ”, 2004 Electronic Components and Technology Conference, 2004, page 4-6.
11. S. Chungpaiboonpatana, F. G. Shi,“Process and Design Analysis for Ultra Fine-Pitched Wire sweep Elimination ”, 2004 Electronic Components and Technology Conference, 2004, page 2-3.
12. H. P. Takiar, P. C. Lin, N. S. Jose,“Stacked multi-chip modules and method of manufacturing”, United States Patent:US05422435, 1995, page 2.
13. W. L. Cheng, H. C. Huang, I. F. Chang, “Package of semiconductor chip of array - type bonding pads”, United States Patent:US06707164, 2004, page 6.
14. 謝文樂, “模組式三次元晶片層疊構裝”, Taiwan Patent:TW00513791, 2001, page 12.
15. 黃建屏, 黃致明, “高電性及散熱性之球柵陣列式封裝結構及其製程”, Taiwan Patent:TW00552689, 2001, page 19.
16. 張欣倫, 許志祥, 黃泰源,“用以於一半導體裝置上形成一重佈層之方法”, Taiwan Patent:TW00594895, 2003, page 24-26.
17. 許詩濱,“形成於積體電路載板電性連接墊之電容結構及其製法”, Taiwan Patent:TW200503146, 2003, page 20.


18. 陳南璋, 林泓均, ``高電性之半導體封裝件及其製法`` (High electric performance semiconductor device and method for fabricating the same), Taiwan Patent:TWI249229, 2004, page 27.
19. 陳炎諄, 陳政郁,吳明傳,``具被動元件之半導體封裝件`` (Semiconductor package with passive component), Taiwan Patent:TWI249824, 2003, page 15.
20. 陳南璋, ``導線架型式半導體封裝件及其製法`` (Lead frame based semiconductor package and fabrication method thereof), Taiwan Patent:TWI249829, 2004, page 25.
21. 許進登, ``具高數量之輸入/輸出連接端之半導體封裝件及其製法`` (Semiconductor package having high quantity of I/O connections and method for making the same), Taiwan Patent:TWI250622, 2003 , page 31.
22. 曹佩華, 蘇昭源, 徐家雄, 黃博德, ``銲線, 其配置, 及該二者的製造方法`` (Method for reducing lead precipitation during wafer processing), Taiwan Patent:TWI251286, 2005, page 17.
23. L. Shen, V. Gumaste, A. Podder and L. Nguyen,“Effect of pad stacks on dielectric layer failure during wire bonding”, (2006 Electronic Components and Technology Conference), 2006, page 2-3.
24. N. Martin and H. Pohjonen,“System-in-Package (SIP) modules for wireless Multiradio”, (2006 Electronic Components and Technology Conference) , 2006, page 2-4.
25. T. Cheng, K. Petrarca, K. Srivastava, S. Knickerbocker, R. Volant, W. Sauter, S. McKnight, S. Allard, F. Beaulieu, D. Restaino and T. Hisada,“Selective Nickel and Gold plating for Enhanced Wire bonding Technology”, (2006 Electronic Components and Technology Conference), 2006, page 2-3.
26. E. Bantog, S. Chiu, C. T. Chen, H. P. Pu and C. S. Hsiao,“Wire Bond, Flip-Chip, and Chip-Scale-Package Solution to High Silicon Integration”, (2006 Electronic Components and Technology Conference), 2006, page 1-3.
27. K. Murayama, M. Higashi, and M. Shimizu,“Investigation of Fundamental Technology for 3D Assembly”, (2006 Electronic Components and Technology Conference), 2006, page 1-2.
28.I. W. Qin, G. Frick,“Providing Process Solutions for Technological Challenges in Hybrid Applications”, (2002 Imasp), 2002, page 4.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內一年後公開,校外永不公開 campus withheld
開放時間 Available:
校內 Campus: 已公開 available
校外 Off-campus:永不公開 not available

您的 IP(校外) 位址是 3.139.103.27
論文開放下載的時間是 校外不公開

Your IP address is 3.139.103.27
This thesis will be available to you on Indicate off-campus access is not available.

紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code