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論文名稱 Title |
ARM10-like微處理器之系統整合與設計驗證方法 Design and verification of an ARM10-like Processor and its System Integration |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
147 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2011-07-20 |
繳交日期 Date of Submission |
2012-02-07 |
關鍵字 Keywords |
微處理器、嵌入式電路擬真器、快取記憶體、協同處理器、整合、驗證 Integration, Embedded in circuit emulator (EICE), Microprocessor, Verification, Cache/MMU, Coprocessor |
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統計 Statistics |
本論文已被瀏覽 5715 次,被下載 5 次 The thesis/dissertation has been browsed 5715 times, has been downloaded 5 times. |
中文摘要 |
隨著半導體製程的技術越來越先進,在相同單位大小的晶片中可容納的硬體IP也越來越多,使得嵌入式系統的功用也日益強大。而在複雜的作業環境中我們需要一顆更有效率的核心處理器來支援整個嵌入式系統的運作,本論文主要目的是針對本實驗室先前已完成實作的一顆仿ARM10微處理器-SYS32TME III,為增加其運算速度、記憶體管理以及提供除錯功能,將整合cache/MMU與Embedded in-circuit emulator (EICE)等模組進入該微處理器。透過cache/MMU模組,我們可以加速微處理器在存取外部記憶體的效能,另外也提供可虛擬化位址以供作業系統(Operating System, OS)使用,其中我們一方面須考慮系統的正確性,另一方面也希望加速系統的整合時間,我們針對與cache/MMU相關的五組功能(cache off, cache on and MMU off with cache hit/miss, cache on and MMU on with cach hit/cache miss and TLB hit/cache miss and TLB miss)逐一進行驗證。針對EICE模組的整合,本論文以coprocessor的六個指令功能( LDC, MCR, MCRR, MRC, MRRC, STC, 在Table 4 1有詳細說明)為主要的驗證項目。在完成個別模組的整合驗證後,我們還進行了微處理器、cach/MMU以及EICE的系統整合回歸測試。最後,將針對整合cache/MMU 與EICE 的微處理器進行效能的調校,在0.18μm製程下提供一個時脈速度200MHz的仿ARM10微處理器。 |
Abstract |
With the advanced of the technique, we can design more IP in the same area space chip. The embedded system has more powerful about its application. We need to have a more efficient core processor to support the whole embedded system in complex system environment. The main purpose of this paper is increased the calculated speed, memory management and debugging for SYS32TME III, which is designed by our lab as an ARM10 like processor. We integrate the cache/MMU and EICE( Embedded in-circuit emulator ) into the embedded processor core. Using the cache/MMU, we can not only speed up the processor which access external memory time but also use the virtual address for Operating System. In order to keep the correctness of the system and speed up the system integration time, we use five functional (cache off, cache on and MMU off with cache hit/miss, cache on and MMU on with cach hit/cache miss and TLB hit/cache miss and TLB miss) tests to verify the cache/MMU and six coprocessor instructions (LDC, MCR, MCRR, MRC, MRRC, STC ) to verify the EICE. After that, we also use the regression test about the microprocessor, cache/MMU and EICE system integration. In the end, we turned the performance about the integrated cache/MMU and EICE, so that we can support an 200MHz ARM 10-like processor by 0.18μm. |
目次 Table of Contents |
Chapter 1. Introduction 1 1.1. Background 1 1.2. Motivation 1 1.3. Research methodology 2 1.4. Contribution 4 Chapter 2. Related work 5 2.1. SYS32TME III microprocessor 5 2.2. Cache/MMU 7 2.2.1. Three simple categories of the cache miss 7 2.2.2. Three design parameters of the cache 8 2.2.3. Memory management 9 2.3. In-circuit emulator (ICE) 11 2.4. Advanced microcontroller bus architecture 14 Chapter 3. SYS32TME III SoC Integration 16 3.1. Top level overview 16 3.2. ICE integration 20 3.2.1. Processor and coprocessor integration 20 3.2.2. Processor and ICE synchronization 25 3.3. Cache/MMU integration 28 3.3.1. Data alignment 29 3.3.2. Cache/MMU 64bits word structure 36 3.3.3. Instruction cache , data cache and MMU synchronied 38 3.3.4. Support 64bits to 32bits wrapper 51 3.3.5. Integration cache/MMU wrapper with SYS32TME III 54 Chapter 4. Verification methodology 64 4.1. Verification environment 64 4.2. Cache Verification 65 4.3. ICE Verification 66 4.4. Verification patterns 67 4.5. Coverage with verification 69 4.5.1. Coprocessor 70 4.5.2. Thumb 70 4.5.3. PC related 70 4.5.4. Interrupts 71 4.6. Case study 72 4.6.1. JPEG Encoder 72 4.6.2. MP3 Decoder 74 4.6.3. MMU/cache testpattern 75 4.6.4. FPGA experiment : uBoot 79 Chapter 5. Synthesis result 82 5.1. Results in UMC 90nm Technology 82 5.1.1. Area analysis 82 5.1.1. Timing analysis 84 5.2. Results in TSMC 0.18μm Technology 86 5.2.1. Area analysis 86 5.2.2. Timing analysis 86 Chapter 6. Conclusion 88 Chapter 7. Future work 90 Reference 91 Appendix A. Major bug list 93 A.1. LDRH 93 A.2. Thumb instructions 93 A.3. Thumb mode branch instruction 94 A.4. Thumb POP 94 A.5. Thumb BL,BLX 95 A.6. Thumb branch instruction 96 A.7. MSR 97 A.8. IRQ interrupt 98 Appendix B. Generate memory by UMC90nm 99 Appendix C. Pattern result 102 Appendix D. Version control system 104 Appendix E. SYS32TME III behavior description 106 E.1. Cache/mmu Request 106 E.2. Data Request through cache 108 E.3. Core fetch instruction 109 E.4. Core fetch data 115 Appendix F. U-BOOT Boot loader command 120 F.1. MEMORY 120 F.2. INFORMATION 125 F.3. NETWORK 130 F.4. BOOT 131 F.5. OTHER 131 |
參考文獻 References |
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