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博碩士論文 etd-0209112-190129 詳細資訊
Title page for etd-0209112-190129
論文名稱
Title
針對遞迴程式中使用者自定及函式庫變數可調整最差與平均時間之高效型草稿記憶體分配器
Efficient Memory Allocation for User and Library Variables in Recursive Programs with WCET/ACET Tunable Performance
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
58
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2012-01-20
繳交日期
Date of Submission
2012-02-09
關鍵字
Keywords
記憶體配置、草稿型記憶體、記憶體建模、函式庫變數、最壞執行時間
memory modeling, memory allocation, library variables, WCET, SPM
統計
Statistics
本論文已被瀏覽 5720 次,被下載 302
The thesis/dissertation has been browsed 5720 times, has been downloaded 302 times.
中文摘要
草稿型記憶體是快取記憶體的另一種替代方案。利用草稿型記憶體,處理器內部高速記憶體(如:靜態隨機存取存儲器)可以直接對映主記憶體位址空間。這樣做有數種好處,記憶體管理單元專門用來做記憶體的配置,藉由移除記憶體管理單元可以減低晶片消耗功率、減少面積,而且草稿型記憶體具有可預測性。在即時系統中,[1]可預測性是很重要的,因為每項工作都必須設定一個期限。如果工作過早結束,那對系統就沒有效益。但如果過晚結束,會導致結果無法預期甚至導致災難。這意味著最壞執行時間比平均執行時間更重要。
跟快取記憶體比較起來,草稿型記憶體需要軟體來支援記憶體的配置。在實驗室先前的研究中[3],針對了最壞情況時間分析編譯設計出一個草稿型記憶體的分配器。
與先前的研究做比照,這篇論文主要有四點貢獻。第一、引進了一個可允許配置函式庫變數進入草稿型記憶體的重要程式碼基礎架構。這種變數在變數存取中占了絕大部分。第二、這篇論文提供對遞迴程式的支援。第三、並且對程式位址計數器相對定址模式的暫存變數也做支援。第四、我們發展出一個用來取得在記憶體行為中精確週期數據的模擬器。在[3]之中,對於進行記憶體配置的成本考量和ARM的複雜的記憶體子系統並沒有設計進去。
關鍵詞:草稿型記憶體、記憶體配置、記憶體建模、函式庫變數、最壞執行時間
Abstract
Scratchpad Memory (SPM) is an alternative to cache. With SPM, the CPU’s fast internal memory (ie, the SRAM) is directly mapped into the memory address space. This has the advantages of reduced power (by avoiding the memory management Unit, MMU, that a cache need to manage its tags and evictions), reduced area (for the same reason), and predictability.[1] Predictability is important in real-time systems, because each task must be assigned a deadline. If a task finishes early, there is no benefit. But if a task finishes late, then the effect is undesirable or even catastrophic. This means that the worst-case execution time (WCET) is more important than average-case execution time (ACET).
The disadvantage of SPM, when compared to cache, is that the SPM requires software management of the fast memory. In a previous student’s work from our laboratory, [3], an SPM allocator was presented for WCET-targeted compilation.
Compared to that work, this current thesis make four key contributions. First, it introduces a significant amount of code infrastructure to allow library variables to be allocated to SPM. These variables turn out to represent a majority of all data accesses in many programs. Second, this provides support for allocating variables within recursive programs. Third, we support allocation of temporary variable (PC-relative addressing). Fourth, we have developed a simulator to obtain cycle-accurate information on memory behavior. In [3], the costs of allocation were not modeled, nor were the behaviors of the ARM’s complex memory subsystem.
Keywords: SPM, memory allocation, memory modeling, library variables, WCET
目次 Table of Contents
Table of Contents
論文審定書...............................................................................................i
中文摘要..................................................................................................ii
英文摘要.................................................................................................iii
Table of Contents.....................................................................................iv
List of Figures ........................................................................................vi
Chapter 1 Introduction 1
1.1 Improvements in Comparison to Our Previous Allocator.................7
1.2 Improvements in Comparison to Other SPM Allocators..................10
Chapter 2 Background Concepts 11
2.1 Measurement-Based Analysis for the Worst-Case Execution Time (WCET).....................................................................................................12
2.2 Static Analysis..................................................................................14
2.3 Concepts of SPM Allocation............................................................16
2.3.1 Frequency per Byte.....................................................................16
2.4 ARM’s Data Transfer Instructions....................................................17
Chapter 3 Related Work 21
3.1 Developing ACET-targeted Optimizing Compiler Methods to Improve the WCET..................................................................................................21
3.2 Developing Specifically WCET-targeted Optimizing Compiler Methods to Improve the WCET................................................................23
3.3 Improving Our Group’s Previous WCET-Aware Allocator............24
Chapter 4 Methodology 26
4.1 Enhancing performance of [3]..........................................................26
4.2 DRAM’s Row Hit or Miss within Memory management issue.......28
4.3Adding Support for ARM’s Addressing Mode Variables..................29
4.4 The Difficulties of Tracing Stack Frame..........................................30
4.5Marking variables’ type in a Realistic Memory Model in the Allocator.................................................................................................35
4.6 Supports for Recursive Programs.....................................................39
4.7 A New Simulator to Replace FacSim...............................................40
Chapter 5 Results 42
5.1 Experimental Environment .............................................................42
5.2 Discussion of Specific Benchmarks.................................................42
6. Conclusions .........................................................................................47
References................................................................................................48
參考文獻 References
References
[1] R. Banakar, S. Steinke, B.S. Lee, M. Balakrishnan and P.Marwedel. “Scratchpad memory: A design alternative for cache on-chip memory in embedded systems”, In Proc. of 10th Intl. Symp. on Hardware/Software Codesign(CODES), pp. 73-78, ACM Press, 2002.

[2] Cheng-Ying Wu. “A Stack-Optimized Scratchpad Memory Allocation for Reducing Either the Average-Case or the Worst-Case Execution”, Master’s thesis: National Sun Yat-Sen University, Kaohsiung, Taiwan, August 2009.

[3] Jia-Yu Bai “A Memory-Realistic SPM Allocator with WCET/ACET Tunable Performance” Master’s thesis: National Sun Yat-Sen University, Kaohsiung, Taiwan, August 2009

[4] V. Suhendra, C. Raghavan, and T. Mitra. “Integrated scratchpad memory optimization and task scheduling for MPSoC Architectures”, in Proc. of the Conference on Compilers, Architecture, and Synthesis for Embedded System (CASES), Seoul, Korea, October 2006.

[5] G. Bernat, A. Colin, and S. M. Petters, “WCET Analysis of Probabilistic Hard Real-Time Systems”, in Proc. of the 23rd Real-Time Systems Symposium (RTSS), Austin, Texas. Dec 2002.

[6] S. Edgar and A. Burns, “Statistical Analysis of WCET For Scheduling”, in Proc. of the 22rd Real-Time Systems Symposium (RTSS), London, United Kingdom. December 2002.

[7] R. Kirner and P. Puschner, “Classification of Code Annotations and Discussion of
Compiler-Support for Worst-Case Execution Time Analysis”, in Proc. of the 5th International Workshop on Worst-Case Execution Time Analysis, Palma, Spain. July 2005.

[8] C. Healy, D. Whalley, and M. Harmon, “Integrating the Timing Analysis of Pipelining and Instruction Caching”, in Proc. of the 16th Real-Time Systems Symposium (RTSS), Pisa, Italy. pp.288-29. December, 1995.

[9] Kim, S., S. L. Min, and R. Ha, “Efficient Worst Case Timing Analysis of Data Caching”, in Proc. of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS), Boston, MA, USA, pp. 230-240. June 1996.

[10] Y. Li, S. Malik, and A. Wolfe, “Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches”, in Proc. of the 17th Real-Time Systems Symposium (RTSS), Washington, D.C., USA, December 1996.

[11] Peter Puschner and Alan Burns, “A review of worst-case execution-time analysis”, Journal of Real-Time Systems, 18(2/3):115–128, May 2000.

[12] J. Lee, J. Kim, C. Jang, S. Kim, B. Egger, K. Kim, and S. Han. “FaCSim: A fast and cycle-accurate architecture simulator for embedded systems,” in Proc. of the ACM SIGPLAN-SIGBED conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Tucson, Arizona, June 2008.

[13] Steve Fuber. “ARM Assembly Language Programming,” in ARM system-on-chip architecture, America, P49-p73.

[14] O. Avissar, R Barua, and D. Stewart. “Heterogeneous Memory Mangement for Embedded Systems”, in Proc. of the Conference on Compilers, Architecturess, and Synthesis for Embedded Systems (CASES), Atlanta, GA, November 2001.

[15] S. Udayakumaran, A. Dominguez, and R. Barua. “Dynamic allocation for scratch-pad memory using compile-time decisions”, ACM Transactions on Embedded Computing Systems (TECS), volume 5, issue 2, p. 472-511. May 2006.

[16] A. Dominguez, S. Udayakumaran, and R. Barua. “Heap data allocation to scratch-pad memory in embedded systems”, Journal of Embedded Computing (JEC), volume 1, issue 4, p. 521-540, IOS Press, Amsterdam, The Netherlands, July 2005.

[17] W. Zhao, B. Cai, D. Whalley, M. Bailey, R. van Engelen, X. Yuan, J. Hiser, J. Davidson, K. Gallivan, and D. Jones. “Vista: a system for interactive code improvement”, in Proc. of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Berlin, Germany, 155–164. June 2002.

[18] W. Zhao, P. Kulkarni, D. Whalley, C. Healy, F. Mueller, and G. Uh. “Tuning the WCET of embedded applications”, in Proc. of the IEEE Real-Time and Embedded Technology and Applications Symposium, Toronto, Canada, p. 472–480. May 2004.

[19] W. Zhao, D. Whalley, C. Healy, and F. Mueller. “WCET code positioning”, in Proc. of the IEEE Real-Time Systems Symposium, Lisbon, Portugal, p. 81–91. December 2004.

[20] W. Zhao, W. Kreahling, D. Whalley, C. Healy, and F. Mueller, “Improving WCET by applying worst-case path optimizations”, Real-Time Systems, volume 34, issue 2, p. 129-152. October 2006.

[21] S. Lee, J. Lee, C. Park, and S. Min. “ A Flexible Tradeoff between Code Size and WCET Using a Dual Instruction Set Processor” , in International Workshop on Software and Compilers for Embedded Systems. Springer, Amsterdam, Netherlands,p. 244-258. September, 2004.

[22] The MiBench Suite. http://www.eecs.umich.edu/mibench/

[23] WCET Benchmarks. http://www.mrtc.mdh.se/projects/wcet/benchmarks.html
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