在即時系統中，為了保證系統的可靠性，每一個程序都必須在時間期限內完成，故在規劃程序的執行順序時提供精確的最差執行時間將會是重要的關鍵。
最差執行時間可以透過測量分析或者靜態分析來獲得，其中測量分析的方式並不能保證最差執行時間的可靠度，故在本論文中我們採用靜態分析的方式以確保最差執行時間的可靠度。
我們使用 SWEET (SWEdish execution time tool) 來提供ARM系統的最差執行時間，但SWEET的記憶體模型過於老舊以至於不能提供精確的最差執行時間。故本論文提供一個簡化的系統架構，對記憶體的寫入以及讀取動作所需要的執行時間做分析。本系統架構除了能夠對DRAM做執行時間的分析,也可以對草稿記憶體做執行時間的分析。除此之外，為了避免記憶體分配器過度最佳化最差執行路徑，本論文亦提供一個較有效率的方式產生近似最差執行路徑。
實驗結果顯示使用我們的記憶體模型來分析記憶體比起假設所有記憶體存取都為最差情況約可以改善43%~46%的最差執行時間。

In order to guarantee the reliability of the real-time system, each process should be complete before the deadline. Therefore, providing accurate WCET for scheduler would be a key factor.
WCET can derive by two method: measurement-base or static analysis. Since measurement-base cannot guarantee the safety of WCET, we use static analysis in this thesis.
In this thesis, we use SWEET (SWEdish execution time tool) to estimates WCET for ARM. Since the memory module of SWEET for ARM is out of date and cannot provide accurate WCET. Therefore, we propose a simplified architecture for analyzing the time costs of memory read accesses and memory write accesses. This method can not only derive the memory access time of DRAM but also SPM. Additionally, in order to prevent over-optimizing issue of allocator on WCET, we also provide a more efficient way to generate nearly worst case flow paths.
Experiment result shows our memory module can improve 43%~46% of WCET compares to the situation which assumed every memory access is worst.

1 INTRODUCTION.......................................................................................1
1.1. REAL-TIME SYSTEMS.............................................................................2
1.2. WORST CASE EXECUTION TIME ANALYZER.........................................3
1.2.1. Measurement-based Analysis ........................................................3
1.2.2. Static WCET Analysis......................................................................5
1.3. ARM SUPPORTED STATIC ANALYZER...................................................6
1.3.1. SWEET Develop by Mälardalen University.......................................6
1.3.2. SWEET Static Analyzer Supported ARM GCC.................................8
1.4. MEMORY MODULE FOR SWEET STATIC-ANALYZER............................9
2. RELATED WORK...................................................................................15
2.1. SWEET ANALYZER................................................................................15
2.1.1. SWEET Flow Analysis Phase.........................................................16
2.1.2. SWEET Low-Level Analysis Phase................................................18
2.1.3. SWEET Calculation Phase.............................................................20
2.2. ARM SUPPORTED SWEET....................................................................24
2.3. MEMORY MODELING............................................................................25
3. METHODOLOGY....................................................................................30
3.1. A DISCUSSION OF THE FACTORS THAT AFFECT THE DRAM ACCESS PATTERN ......................................................................................................30
3.2. THE SPECIFIC IMPACT OF THE IPB UPON THE MEMORY ACCESS ORDER..........................................................................................................32
3.3. DERIVING THE MEMORY AWARE WCET...............................................37
3.3.1. Deriving the Worst-case Time for Reads, WTOR...........................38
3.3.2. Deriving the Worst-case eXtra Time for Writes, WXTW..................44
3.3.3. A Discussion of Optimizations for Improving the WCET Quality and the Analysis Time for Our Algorithm ..............................................................54
3.4. PRODUCE THE NECFP..........................................................................58
4. EXPERIMENTS RESULTS......................................................................60
5. CONCLUSIONS......................................................................................64
6. REFERENCE.........................................................................................65

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