電子封裝產品之可靠度測試一直以來皆為電子業界導入新產品的重要指標，其測試結果直接影響產品實際運用及市場需求。目前全球環保組織對無鉛製程已有明確規範，電子產品勢必將全面導入無鉛製程及材料，對於無鉛製程的研究改善更甚重要。本研究導入目前現階段使用於晶圓級產品- Ultra CSP 的無鉛錫球產品，進行可靠度分析、測試。
導入測試的無鉛錫球共有 Sn/Ag4.0/Cu0.5、Sn/Ag2.6/Cu0.6 與Sn/Cu0.75 三種材料。其中 Sn/Ag4.0/Cu0.5 使用兩種不同理論的迴焊加熱曲線作分析比較。實驗目的主要在於研究迴焊加熱曲線改善的導入可行性及對產品影響，另外其產品經過可靠度測試後的機械性質 趨勢，配合 IMC 的觀察，從而獲得改善無鉛產品可靠度的方法與無鉛材料的特性。由實驗結果得知:
Sn/Ag4.0/Cu0.5 錫球於使用改善後的迴焊加熱曲線於裸晶片測試後錫球剪力測試值與原製程產品相比於 HTST、TCT 及 TST 項目中在 500 cycles循環測試後，錫球剪力測試值大於原製程產品，顯示抗疲勞性較佳。而完整封裝晶片測試 (Board Level Test) 結果則顯示增加 144 cycles 的週期。
使用 Sn/Ag2.6/Cu0.6、Sn/Ag4.0/Cu0.5 無鉛錫球的產品，兩者在Package Level Test 與 Board Level Test 均有相近的測試值。

1.Sn/Ag4.0/Cu0.5 solder with better performance by the improved reflow profile.
2.The Sn/Ag2.6/Cu0.6、Sn/Ag4.0/Cu0.5 with similar reliability test performance.

LIST OF FIGURE CAPTIONS III
LIST OF TABLE CAPTIONS VI
LIST OF ACRONYMSI VII
CHINESE ASTRACT XI
CHAPTER 1 INTRODUCTION1
1-1 Background 1
1-2 Wafer level package assembly technology 4
1-3 Structure analysis 8
1-4 Process parameter analysis 13
1-5 The research and development direction 14
CHAPTER 2 RELIABILITY TEST 16
2-1 Reliability test 16
2-2 The test items for reliability 20
2-2-1 Precondition test 20
2-2-2 Temperature cycle test 21
2-2-3 High temperature storage test 23
2-2-4 Pressure cooker test 23
2-2-5 Highly Accelerated Temp & Humidity Stress test 24
2-3 The failure mode evaluation methods of reliability test 25
CHAPTER 3 EXPERIMENT DESIGN 27
3-1 Test equipment 27
3-2 Board level test sampler 29
3-3 Test items 29
3-3-1 Bare die test 29
3-3-2 On-board test evaluation 32
3-3-3 Solder sphere shear test 33
3-3-4 Test samplers grinding and polishing 33
3-3-5 The analysis by the Scanning Electronic Microscope
(SEM) 33
CHAPTER 4 TEST RESULTS 41
4-1 Package level test 41
4-1-1 The reflow profile optimization for Sn/Ag4.0/Cu0.5
41
4-1-2 The SAT test items 42
4-1-3 The sphere shear test after package reliability items
42
4-1-4 The IMC growing status evaluations 44
4-1-5 The metal distribution evaluations 45
4-2 Board level test 45
CHAPTER 5 CONCLUSIONS 66
5-1 Conclusions 66
5-2 Future research topics 67
BIBLIOGRAPHY 68






LIST OF FIGURE CAPTIONS

Fig.1-1 Comparison among different packages 5
Fig.1-2 Applied for memory EEPROM 6
Fig. 1-3 Products applied with Wafer level package 6
Fig. 1-4 The total forecast of CSP package type distribution 2001- 2006 9
Fig.1-5 Wafer level CSP forecast turnover and total volume 9
Fig.1-6 BCB (BenzoCycloButene) monomer structure 10
Fig.1-7 Basic wafer structures 12
Fig.2-1 Bathtub curve of the life period 17
Fig.2-2 Crack caused by solder fatigue 19
Fig.2-3 TCT cycle time VS temperature profile 22
Fig.2-4 TCT influence in package 22
Fig.2-5 Production corrosion after PCT 24
Fig.3-1 Bare die test flow and items description 31
Fig.3-2 Process flow for Board level TCT test 32
Fig.3-3 The appearance of bare die 34
Fig.3-4 Dage 2400A shear test machine 35
Fig.3-5 The X-ray equipment 35
Fig.3-6 Sikama SBM360 reflow 36
Fig.3-7 Test board 36
Fig.3-8 Test sample on board 37
Fig.3-9 Grinding and polishing machine 37
Fig.3-10 SEM & EDX machine 38
Fig.3-11 The SAT machine 38

Fig.3-12 Optical microscope 39
Fig.3-13 The reflow profile curve 39
Fig.3-14 Cross-sectional view structure of solder sphere 40
Fig.3-15 Solder sphere shear simulation diagram 40
Fig.4-1 The X-ray inspection photo for Sn/Ag4.0/Cu0.5 in reflow profile
(a) right site (b) left site (c) up site (d) down site ………………………… 48
Fig.4-2 The X-ray inspection photo for Sn/Ag4.0/Cu0.5 in reflow profile (a) right site (b) left site (c) up site (d) down site 49
Fig.4-3 (a) Solder composition Sn/Ag2.6/Cu0.6 SAT photo 50
Fig.4-3 (b) Solder composition Sn/Cu0.75 SAT photo 51
Fig.4-3 (c) Solder composition Sn/Ag4.0/Cu0.5 processed in the 1st
reflow SAT photo 52
Fig.4-3 (d) Solder composition Sn/Ag4.0/Cu0.5 processed in the 2nd
reflow SAT photo 53
Fig.4-4 (a) TST and HTST shear value tendency and CPK chat 55
Fig.4-4 (b) THT and PCT shear value tendency and CPK chat 56
Fig.4-4 (c) TCT shear value tendency and CPK chat 57
Fig.4-5 IMC status and shear failure mode for lead free solder 58
Fig.4-6(a) IMC status for lead free solder by SEM 59
Fig.4-6(b) IMC thickness comparison, for Sn/Ag4.0/Cu0.5 in reflow
profile 1 and profile 2 during TCT 300 cycles 60
Fig.4-6(c) IMC thickness comparison, for Sn/Ag4.0/Cu0.5 in reflow
profile 1 and profile 2 during TCT 1000 cycles 61
Fig.4-7(a) EDX analysis for Sn63/Pb37 and Sn/Ag2.6/Cu0.6 62
Fig.4-7(b) EDX analysis for Sn/Ag4.0/Cu0.5 and Sn/Cu0.75 63
Fig.4-7(c) EDX analysis for Sn/Cu0.75 64
Fig.4-8 Board level test result 65


























LIST OF TABLE CAPTIONS

Table 1-1 Common lead free alloy metals 3
Table 1-2 Comparison table with Flip Chip package 7
Table 2-1 Items of ASE reliability test 26
Table 4-1 The reliability tests result 47
Table 4-2 Solder sphere shear value 54



























LIST OF ACRONYMS

1 ASE Advanced Semiconductor Engineering company
2 BCB BenzoCycloButene material
3 BGA Ball Grid Array Package
4 CSP Chip Scale Package
5 DAS Data Analysis System
6 DNP The Distance to Neutral Point for package
7 EIAJ Electronic Industries Alliance Japan
8 FCOB Flip Chip On Board
9 FCT Flip Chip Technologies company
10 FITS Failure In Times
11 HTST High Temperature Storage Test
12 IC Integrated Circuit
13 IMC Intermetallic Compound
14 JEDEC Joint Electron Device Engineering Council
15 MEMS Micro-Electro Mechanical System
16 MOEMS Micro-Optical Electro Mechanical System
17 MTBF Mean Time Between Failure
18 MTTF Mean Time To Failure
19 PCT Pressure Cooker Test
20 RDL Repeat Distribution Layer structure
21 RoHS Restriction of Hazardous Substances
22 SAT Scanning Acoustic Tomogram
23 SEM Scanning Electronic Microscope
24 SMT Surface Mount Technology
25 TCT Temperature Cycling Test
26 THB Temperature Humidity Bias Test
27 TSOP Thin Small Outline Package
28 TST Thermal Shock Test
29 UBM Under Bump Metallurgy
30 WBGA Wire Bounding Ball Grid Array package
31 WCSP Wire Bounding Chip Scale package
32 WEEE Waste Electrical and Electronic Equipment
33 WLP Wafer Level Package

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2. V. Patwardhan, N. Kelkar, and L. Nguyen “Lead-Free Wafer Level-Chip Scale Package: Assembly and Reliability” Electronic Components and Technology Conference (2002)

3. S.J. Cho, J.Y Kim, Myung-Geun Park “Under Bump Metallurgies for a wafer Level CSP with Eutectic Pb-Sn Solder ball” Electronic Components and Technology Conference(2000)

4. T. Hirano, K. Fukuda, K Ito, T.Kiga, Y. Taniguchi “Reliability of Lead Free Solder Joint by Using Chip Size Package” Electronic Components and Technology Conference (2001)

5. European Union Waste in Electrical and Electronic Equipment（WEEE）Directive, 3rd Draft, May 2000.

6. Yifan Guo, Jong-Kai Lin ,Anada De Silva “Reliability Evaluations of Chip Interconnect in Lead-Free solder systems” Electronic Components and Technology Conference(2002)

7. H Gan, KN Tu “Effect of Electromigration on Intermetallic Compound Formation in Pb-free Solder- Cu Interfaces” Electronic Components and Technology Conference (2002)

8. Kulicke & Soffa com “Spheron WLP” May 2002.

9. Hong Yang, Alan Larson, Scott Barrett, Peter Elenius “Reliabilty Evaluation of UltraCSP packages” Components and Technology Conference (2001).

10. D.H. Kim, P. Elenius, and S. Barrett “Solder Joint Reliability and Characteristics of Deformation and Crack Growth of Sn-Ag-Cu Versus Eutectic Sn-Pb on a WLP in a Thermal Cycling Test” IEEE Electronic Components and Technology Conference (2002)

11. eformation and Crack Growth of Sn-Ag-Cu Versus Eutectic Sn-Pb on a WLP in a Thermal Cycling Test” IEEE Electronic Components and Technology Conference (2002)

12. D. H. Kim, P. Elenius“Deformation and Crack Growth Characteristics of SnAgCu vs 63Sn/Pb Solder Joints on a WLP in Thermal Cycle Testing” IMAPS Electronic Components and Technology Conference(2001)


13. K&S Flip Chip Division ” UltraCSP Lead Free Process release“
Patent release paper, June 2002

14. FCD “ FCT Reliability manual ” Electronic Components and Technology Conference (2001) Reliability part I, pp.10-14.

15. Dow Chemical “ Technical data of Benzocyclobutene-based Ploymer “ (2001)

16. 劉立晟“ Flip-Chip Ball Grid Array Lead Free Solder Joint under Reliability Test” 碩士論文，中山大學機械與機電研究所 2003, pp.55-59.

17. National semiconductor “Mounting of Surface Mount device” (Aug.2000)