本論文主要實現一個有八個輸入通道具有延遲相加功能的特殊應用積體電路(ASIC)，這是實現低功耗並應用於處理神經訊號之速度選擇紀錄裝置的基本架構，此系統主要將神經環的訊號藉由雙差動放大器後進行處理，匹配速度的選擇以及取樣速率由外部提供的時脈訊號控制。本晶片包含由輸入時脈訊號控制的取樣時脈訊號產生器、四組內含八個取樣保持電路且具加總作用的延遲相加電路、一個輸出緩衝器、及一些相關的控制訊號單元。此晶片主要實現在台積電0.35 μm
製程之下。該論文中包含兩個版本，此兩版本的差別在於訊號產生區塊內的除頻電路，加上除頻電路的第二版本提供更好的取樣效率，並改善了佈局技巧，使得第二版本有更小的面積。該兩版本面積分別為850 μm*450 μm 以640 μm*390 μm。該論文中也包含兩版本的模擬結果。在第二版本的測量結果方面顯示在供應電壓為3.3V 且時脈訊號產生區塊正常工作之下的功耗為170μW。

This thesis describes the design and evaluation of an integrated circuit (ASIC) implement eight parallel signal channels providing analog-amplitude delay-and-add functionality. This implementation is a fundamental building block towards the future realization of a low-power velocity-selective-recording arrangement (VSR) for the processing of the peripheral neurogram. The system is intended to operate with preamplified nerve signals acquired in the true-tripole configuration using an implanted nerve cuff. The matched velocity and sample rate are controlled by externally supplied digital clocks. The ASIC contains the clock phase generators (which use the suppliedclocks as reference), four capacitance-based sample-and-hold sections each consisting of eight sampling cells with summation functionality, an output buffer, and supporting control units. The circuits were fabricated in TSMC 0.35 μm CMOS technology. Two slightly different versions of the integrated system are reported. The second version adds an on-chip frequency divider to achieve more finely controlled sample settings and it improves the layout. The active area is about 850 μm*450 μm and 640 μm*390 μm respectively. Both systems are evaluated in transistor-level simulation. Moreover, bench test measured results for the second version system are presented which confirm the correct operation of the on-chip generated timing signals and a measured power consumption of 170 μW using a 3.3V supply.

Contents
摘要………………………………………………………………….…....i
Abstract…………………………………………....………………..…..ii
Content…………………………………………………………………..iv
List of Figures……………………………………………………….....vii
List of Tables…………………………………………………………..xiii
Chapter 1 Introduction…………………………………………………1
1.1 Background and motivation………………….…………………..1
1.2 Application of the VSR system……………………….…...……3
1.3 Specification requirements..………………………….……....…4
1.4 Contributions of this thesis……………………………………....5
Chapter 2 Signal Model……………………………………………….6
2.1 The Model of the Tripolar Electrode Potential….....…………..6
2.2 Recording Configurations……….……………………………....10
Chapter 3 Circuit Design………………………………………….….10
3.1 Sample-and-Hold Delay Stage……………………….…………14
3.2 Clock Signal Generator for Delay Stage…………………....…16
3.3 Sample Signal and Summing Signal Generator Circuit……...20
3.4 Output Multiplexer Stage………………….………………….…22
3.5 Buffer stage…………….………………………………………...25
3.6 Complete Processor Circuit……………………….…………….27
Chapter 4 Simulated Results………………………………….…….31
4.1 Sample and summation clock generator…………….………..32
4.2 Capacitor columns……………………….……………………...35
4.3 Multiplexer block…………………………….…………..………38
4.4 System evaluation…………………….………………………...41
4.5 Delay tuning curve…………………………….………….……..42
4.6 Chip layout…………………….……………………………..…..50
Chapter 5 Measured Results………………………………………..53
5.1 Microscope image of the chip………………………..….……..53
5.2 Clock generator measurement……………….……..………….55
5.3 Comparison………………………….…………………..……….72
Chapter 6 Conclusion…………………………………..……………73
6.1 Conclusion……………….....……………………….…………..73
6.2 Future work……………………………….…………..………….73
List of References……………………………………..…………….75

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