以可重組態運算系統來加速程式執行效能已成為許多高效能運算平台的運作模式。因此，使用微處理器結合可重組運算單元作為嵌入式系統實現的平台已逐漸成為一種趨勢。然而，透過微處理器結合擁有硬體可重配置的邏輯電路來加速系統效能，在現今嵌入式軟硬體設計與整合上, 對於設計者是一大挑戰；而軟硬體間的溝通方式更是系統能否有效率運作的關鍵。本論文針對可重組態運算系統設計，建立I-Link軟硬體檔案整合環境來提升軟硬體間的整合度和方便性。並且以簡單地傳送指令封包方式快速地將資料透過硬體管理單元(HMU)對多個硬體作存取。系統啟動時，可透過開機流程依據程式前置區(PSP)建立TCB以及HCB資料結構區端。PSP資訊區可作為系統與軟硬體間資訊交換的重要參考區端，而HMU的特色即是擁有資料緩衝與管理的能力，可讓資料流通更為流暢。我們成功地將軟硬體整合系統實現於實驗室所開發的平台(HSCP)。平台之基本元件主要包含ARM7TDMI CPU、記憶體以及Altera ACek 1K-100的FPGA。成功地利用ARM組合語言初步完成開機程式(Bootloader)、HW Constructor以及自行開發的嵌入式作業系統。最後，我們利用大量乘法運算與矩陣相加來驗證本系統架構的可行性。

Reconfigurable supercomputing has been used by many high-performance computer systems to accelerate the processing speed. Thus, it is the present trend to use the microprocessor to combine with reconfigurable FPGA as the embedded system platform. However, the hardware-software co-design and integration of embedded system become great challenges of the designer. Beside this, the communication between hardware and software is crucial for the system to be operated effectively. Our concept consists of the design of FPGA configuration, described in I-Link hardware/software integration, improve the communication among the hardware and software. Besides, by using command packet method, we put the data to multi-hardware through hardware management unit (HMU). While system is operated, The Boot Loader will set up TCB and HCB data structure through PSP. The PSP can be regarded as the important reference segment of messages switching among system and hardware/software. The HMU has data buffering and management ability which can let the processes more easy and smooth. We successfully accomplish a hardware-software integrated system in HSCP, which is developed in our laboratory. The basic components of our platform include ARM7TDMI CPU, memory and Altera ACEK 1K-100 of FPGA. By using ARM-code, we also preliminary accomplish the Boot Loader, HW Constructor and self-developed embedded system. Finally, we make use of a large amount of multiplication operation and matrix summation to verify the feasibility of this system architecture.

目錄
摘要 2
ABSTRACT 3
第一章 簡介 7
1-2 研究動機 . 8
1-3 研究目的 9
1-4 論文架構 9
第二章 相關研究 11
2-1 FPGA實現軟硬體協同設計背景 11
2-2 軟硬體協同設計與系統規劃 19
2-2.1 VForce 系統架構 19
2-2.2 STARSoC架構於軟硬體溝通介面 21
2-2.1 MPSoC自動產生軟硬體溝通介面平台 23
2-3可重新組態運算系統之相關研究 26
2-4 結論與分析 29
第三章 軟硬體整合平台建設 30
3-1 I-Link的建立 30
3-2 Task PSP的區端規劃 32
3-3 Netlist PSP的區端規劃 34
3-4 PSP在記憶體中的規劃 35
3-5 平台的基本組件與連接 37
3-6平台運作模式 46
3-7 開機流程 48
3-8 系統記憶體規劃 51
第四章 硬體管理單元設計 57
4-1軟硬體協同設計架構 57
4-2硬體管理單元 60
4-2.1 HMU位址解碼單元 61
4-2.2 HMU內部控制單元 61
4-2.2記憶體存取結構 64
4-2.3 HMU內部仲裁器 68
4-3硬體函式呼叫指令 70
第五章 系統實現與驗證 73
5-1 系統實現 73
5-2 系統驗證與分析 76
第六章 結論與未來方向 86
參考資料 87

圖目錄

圖2-1.1(a) PPA下載方式電路 11
圖2-1.1(b) PPS下載方式電路 11
圖2-1.1(c) PS Timing Waveform 12
圖2-1.1(d) PPS Timing Waveform 13
表2-2.1 FPGA上設定用Pin腳功能 14
圖2-1.1(e) 以Bus Switch做為FPGA設定訊號 與PIO之間的開關 15
圖2-1.1(f) 以PIO對FPGA進行設定之流程圖 16
圖2-1.2 JTAG設定方式電路圖 17
圖2-2.1 Vforce Framework架構 20
圖2-2.2(a) STARSoC設計流程 21
圖2-2.2(b) STARSoC ─ CPU與單一硬體溝通方式 21
圖2-2.2(c) STARSoC ─ CPU與多個硬體溝通方式 22
圖2-2.3(a)(b) MPSoC ─ 記憶體映射架構 23
圖2-2.3(c) MPSoC─ 平台上之系統架構 24
圖2-2.3(d) MPSoC─ 於RTL層級實現軟硬溝通流程 25
圖2-3 MorphoSys架構 27
圖3-1 I-Link的建立 30
圖3-2(a) Task PSP格式 32
圖3-2(b) Task PSP範例 32
圖3-2(c) TCB Table的建立 33
圖3-3(a) Netlist PSP格式 34
圖3-3(b) Netlist PSP範例 34
圖3-3(c) Command Table的建立 34
圖3-4 PSP的規劃與連接 36
圖3-5(a)實驗平台主體架構 37
圖3-5(b)外部Flash Memory與CPU之連接 39
圖3-5(c) FPGA控制訊號的連接 40
圖3-5(d) FPGA上記憶體介面模擬波形 41
表3-5 EBI外部裝置存取時脈 42
圖3-5(e) 加上Bus Switch後FPGA與Data Bus之連接 43
圖3-5(f) Standard Read Protocol 44
圖3-5(g) Early Read Protocol 45
圖3-5(h) FPGA介面存取實測時序圖 45
圖3-6 開機模式切換流程 47
圖3-7系統與外部硬體溝通方式 50
圖3-8(a) 記憶體的規劃 51
圖3-8(b) ROM的記憶體配置 51
圖3-8(c) RAM的記憶體配置 51
圖3-8(d) MCU主記憶體的規劃 52
圖3-8(e) ARM7三階管線 55
表4-1 Vforce2 和 HSCP的差異 57
圖4-1嵌入式系統主體架構 58
圖4-2(a) 硬體管理單元之主體架構圖(HMU) 59
圖4-2(b) HMU之輸入位址封包格式 60
表4-2.1(a) 硬體管理單元之狀態列表(LAT) 61
表4-2.1(b) 硬體的單筆輸入頻寬定義 62
表4-2.2 FIFO狀態列表 64
圖4-2.2(a) 16-bit taggedFIFO的內部結構 65
圖4-2.2(b) taggedFIFO之緩衝評估 66
圖4-2.2(c) 8個16-bit taggedFIFO元件接線圖 66
圖4-2.3(a) HMU與硬體間傳輸協定 68
圖4-2.3(b) 4x4 ROUND-Robin輸入仲裁器 69
表4-2.3 4x4 ROUND-Robin真值表 69
圖5-1 I-Link下載介面 74
表5-1.1 ROM的記憶體內部資訊 74
圖5-2 TID = 0 之4x4矩陣相加模擬波形圖 78
圖5-2.1 TID = 1 之4x4矩陣相加模擬波形圖 80
圖5-2.2 HMU之4x4矩陣所需之邏輯閘數目 81
圖5-2.3 HMU之4x4矩陣所需之邏輯閘數目 81
圖5-2.4 4x4矩陣換算在HSPC實驗平台上的驗證 82
圖5-2.5 乘法換算模擬波形 84

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