因為可編程之圖形處理單元經常等待長延遲指令的執行結果而閒置，為了增加使用率，多執行緒的技術常被採用於設計當中。本論文提出的多執行緒之統一圖形處理單元設計，擁有下列幾項特點。第一點，處理核心不僅可以執行頂點著色器與像素著色器，還可以執行用軟體實作的點陣化模組；在其它的圖形處理單元設計中，點陣化模組大部分是使用額外的硬體去實作。此外，我們的設計所採用的執行緒切換策略為不可搶先的阻塞式排程法。通常，一個指令在進入指令解碼階段之前，無法被得知是否會拖延整個程式的執行。為了達到零花費的執行緒切換，一個協助位元被增添於每個指令中，告知控制單元相同執行緒內的下個指令是否會拖延程式的執行。這個機制在本論文所跑的某些測試程式中可以達到1.4倍的加速。圖形處理單元所用的暫存器一般可到四個存取埠，在多執行緒的設計中，由於暫存器會複製好幾份，佔圖形處理單元相當大的部份。基於本論文所提出的方法，使用多塊兩埠的暫存器來取代一般的暫存器設計，可以減少硬體實作的花費。我們的實驗結果顯示這個方法可以減少約整體26.12%的邏輯閘。最後，為了進一步減少面積，剩下的固定化管線之像素運算模組採用分時架構來實現。而本文所提出的圖形處理單元的邏輯閘總數為600K。

In order to increase the data-path utilization of the programmable graphics processor units (GPU) which often stall by waiting for the execution results of those long-latency instructions, multi-thread technique is very often used in the design of GPU. This thesis proposes a multi-thread single unified core GPU design which owns several key features. First, its processor core can execute not only the vertex and fragment shading programs, but also the software rasteriation module which is mostly implemented by a individual hardware module in other GPU designs. Next, the thread-switching policy in our design is based on the non-preempt blocked scheduling. Normally, whether an instruction will be stalled cannot be detected until it enters the instruction-decode stage. In order to achieve zero-penalty thread switching, a single assistant bit will be padded to each instruction in a thread to tell if the next instruction in the same thread will be stalled or not. This mechanism can help achieve a speed-up of 1.4 in some benchmarks used in this thesis. The register file used in GPU processor is usually equipped with up to four access ports, such that it will occupy a significant portion of the entire GPU especially for muti-thread designs where the register set has to be duplicated by several copies. The implementation cost of the register file can be reduced by decreasing its access port number to two based on the proposed multi-bank approach in this thesis. Our experimental results show that this approach can help reduce the overall gate count by 26.12%. Finally, the rest of fixed-pipeline fragment operation is realized by an iterative time-sharing architecture in order to further save the silicon area. The overall gate count of the proposed GPU is 600K.

CHAPTER 1 概論....................................................................................1
1.1 研究動機......................................................................................1
1.2 論文大綱......................................................................................1
CHAPTER 2 研究背景與相關研究........................................................3
2.1 三維圖學簡介與流程..................................................................3
2.1.1 幾何轉換與著色子系統簡介.............................................3
2.1.2 可程式化三維繪圖架構.....................................................9
2.1.2.1 頂點與像素處理器簡介........................................10
2.1.2.2 統一處理器簡介....................................................13
2.2 多執行緒處理器相關背景........................................................16
2.2.1 多執行緒處理器架構介紹................................................17
2.2.2 多執行緒排程策略介紹...................................................24
CHAPTER 3 三維後端呈像子系統設計...............................................26
3.1 像素處理器說明與設計..........................................................26
3.1.1 指令集功能說明...............................................................26
3.1.2 硬體架構...........................................................................29
3.2 Per-fragment operation 說明與設計.......................................35
3.2.1 OpenGL ES 2.0 功能說明與硬體設計..........................36
CHAPTER 4 多執行緒之統一處理器說明與設計..............................40
4.1 Unified fragment operation unit 設計......................................40
4.2 Unified GPU 設計...................................................................43
4.2.1 硬體架構...........................................................................43
4.2.2 多執行緒機制與排程策略...............................................50
4.2.3 處理器儲存元件分析.......................................................53
CHAPTER 5 系統實作成果..................................................................58
5.1 功能驗證....................................................................................58
5.1.1 軟體驗證...........................................................................58
5.1.2 硬體驗證...........................................................................58
5.1.2.1 RTL 驗證...............................................................58
5.1.2.2 Co-sim 驗證...........................................................58
5.1.2.3 FPGA 驗證............................................................59
5.1.3 執行結果...........................................................................60
5.2 系統介面與定址空間................................................................61
5.3 合成數據與效能分析................................................................63
CHAPTER 6 結論與未來目標..............................................................66
6.1 結論............................................................................................66
6.2 未來目標....................................................................................66

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