本論文針對兩種常用的錯誤更正碼提出低功率的硬體架構，首先設計一基於參考路徑之低功\\\率的腓特比解碼器，其作法為減少回溯動作所需的記憶體讀取次數。在過去的文獻中參考路徑機制已被提出，本論文主要針對回溯路徑和預測路徑起始點的選擇做進一步的探討，根據模擬顯示當以最小狀態當作回溯路徑和預測路徑起始點有最好的實驗結果，92%記憶體讀取動作可被減少。然而，當腓特比解碼器使用的狀態數較多時，以最小狀態當起始點配合前看式路徑預測演算法的作法在實作上將會造成硬體面積的負擔，因此，本論文設計基於64個狀態腓特比解碼器並以上一次的預測狀態當作起始點來建構預測路徑。根據實驗結果，我們設計的硬體其電路佈局只比傳統腓特比解碼器多了10%的晶片面積，但可減省31%~47%的功率消耗。本論文的第二個主要貢獻為將此低功\\\率技術用於渦輪解碼器中的軟式輸入輸出腓特比解碼器，據實驗結果在基於八個狀態軟式輸入輸出腓特比解碼器的渦輪解碼器，我們的參考路徑機制可減少95%以上的記憶體讀取次數，其電路佈局只比傳統渦輪解碼器多了3%的晶片面積，卻可減省15.6%的功率消耗。

In this thesis, the low-power design of two popular error-control code decoders has been presented. It first proposes a low-power Viterbi decoder based on the improved reference path generation method which can lead to significant reduction of the memory accesses during the trace-back operation of the survival memory unit. The use of the reference path has been addressed in the past; this mechanism is further extended in this thesis to take into account the selection of starting states for the trace-back and path prediction operations. Our simulation results show that the best saving ratio of memory access can be up to 92% by choosing the state with the minimum state-metric for both trace-back and path prediction. However, the implementation of our look-ahead path prediction initiated from the minimum state will suffer a lot of area overhead especially for Viterbi applications with large state number. Therefore, this thesis instead realizes a 64-state Viterbi decoder whose path prediction starts from the predicted state obtained from the previous prediction phase. Our implementation results show that the actual power reduction ratio ranges from 31% to 47% for various signal-to-noise ratio settings while the area overhead is about 10%. The second major contribution of this thesis is to apply the similar low-power technique to the design of Soft-Output-Viterbi-Algorithm (SOVA) based Turbo code decoders. Our experimental results show that for eight-state SOVA Turbo code, our reference path generation mechanism can reduce more that 95% memory accesses, which can help saving the overall power consumption by 15.6% with a slight area overhead of 3%.

論文審定書 i
中文摘要 ii
英文摘要 iii
第 一 章 序論 1
1.1研究動機 1
1.2論文大綱 2
第 二 章　腓特比演算法的介紹 4
2.1 迴旋碼 4
2.2 腓特比解碼器 5
2.2.1 Branch metric unit (BMU) 7
2.2.2 Add Compare Select Unit (ACSU) 8
2.2.3 Survivor memory Unit (SMU) 10
2.3基於參考路徑的回溯追蹤法 13
第 三 章 基於參考路徑對照之低功率腓特比解碼器 19
3.1回溯起始點和預測路徑起始點選擇之探討 19
3.2 結果分析 21
3.3 基於參考路徑腓特比解碼器之架構設計 27
3.3.1 一級前看式預測路徑演算法的硬體架構 27
3.3.2 找出最小狀態之硬體架構 28
3.3.3基於參考路徑腓特比解碼器的整體架構 31
第 四 章 渦輪碼原理 33
4.1 渦輪編碼器 33
4.1.1 RSC編碼器 33
4.1.2 交錯器 35
4.2 渦輪解碼器 36
4.3 SOVA演算法 36
4.4 TWO-Step SOVA演算法 38
第 五 章 渦輪碼之架構設計 40
5.1 Two-Step SOVA 之架構 40
5.1.1 BMU架構 (Branch Metric Unit) 41
5.1.2 ACSU架構 (Add-Compare-Select Unit) 42
5.1.3 Max_find架構 43
5.1.4 Prediction架構 44
5.1.5 SMU架構 44
5.1.6 PCU (Path Comparision Unit)架構 47
5.1.7 RMU (Reliability Measure Unit)架構 47
5.1.8 A-post LLR 48
5.2 渦輪解碼器硬體架構 48
第 六 章 模擬結果分析 50
6.1 模擬流程 50
6.2 模擬結果比較 50
第 七 章 結論 59
參考文獻 60

[1] G. D. F. Jr., “The Viterbi algorithm,” in Proc. IEEE, vol. 61, March 1973, pp. 268–278.
[2] C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon limit error- correcting coding and decoding: Turbo-codes,” in Proc. IEEE Intl. Conf. on Comm., Geneva, May 1993, pp.1064–1070.
[3] “IEEE 802.16e-2005, IEEE standard for local and metropolitan area network - part 16: Air interface for fixed and mobile broadband wireless access systems - amendment 2: Physical and medium access control layers for combined fixed and mobile operation in licensed bands.”
[4] ETSI, Digital Video Broadcasting (DVB); Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television, EN 300 744 V1.4.1., Jan. 2001.
[5] C. Tsui, R. S.-K. Cheng, and C. Ling, “Low power ACS unit design for the Viterbi decoder,” in Proc. IEEE ISCAS, Florida, May 1999, pp. 137–140.
[6] M. Guo, M. O. Ahmad, M. N. S. Swamy, and C. Wang, “FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2, pp. 350–365, Feb. 2005.
[7] F. Sun and T. Zhang, “Low-power state-parallel relaxed adaptive Viterbi decoder,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 5, pp. 1060–1068, May 2007.
[8] C.-C. Lin, Y.-H. Shih, H.-C. Chang, and C.-Y. Lee, “Design of a power reduction Viterbi decoder for WLAN applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 6, pp. 1148–1156, June 2005.
[9] M.-B. Lin, “New path history management circuits for Viterbi decoders,”IEEE Trans. on Communications, vol. 48, no. 10, pp. 1605–1608, Oct. 2000.
[10] G. Feygin and P. G. Gulak, “Architectural tradeoffs for survivor sequence memory management in Viterbi decoders,” IEEE Trans. on Communications, vol. 41, no. 3, pp. 425–429, Mar. 1993.
[11] R. Cypher and C. B. Shung, “Generalized trace-back techniques for survivor memory management in the Viterbi algorithm,” in Proc. Globecom, California, vol. 2, Dec. 1990, pp. 1318–1322.
[12] C.C Lin, C.C. Wu,and C.Y Lee,” A low power and high speed Viterbi decoder chip for WLAN application,” in Proc. ESSCIRC, Sep. 2003, pp. 723-726.
[13]丁昱中, “Design and Implementation of Low-Cost Dual Mode Channel
Decoder”, Master Thesis, National Sun-Yat-Sen University, July 2003.
[14] J. Hagenauer and P. Hoeher, “A Viterbi algorithm with soft-decision outputs and its applications,” in Proc. of IEEE Globecom, Texas, vol. 3, pp. 1680–1686, June 1989.
[15] C. Berrou, P. Adde, E. Angui, and S. Faudeil, “A low complexity soft-output Viterbi decoder architecture,” in Proc. Int. Conf. Communications, Geneva, May 1993, pp. 737–740.