本篇論文設計了可以計算128/256/512/1024/2048的可變長度快速傅立葉轉換處理器晶片，這顆晶片採用單一路徑延遲迴授(single-path delay feedback)的管線(pipeline)架構配合Radix-2^3演算法來做設計，並且透過系統模擬來決定表示資料所需的位元數，以達到正交分頻多工傳輸系統的需求。除此之外，我們提出了一個迴授旋轉因子產生器用來替代存放旋轉因子儲值表(lookup table)，以節省所需的記憶體空間。
在使用CMOS 0.35μm 2P4M製程的情況下，我們的快速傅立葉轉換處理器其核心面積只有3.381 x 3.3625 mm^2，而且經過後佈局模擬(post-layout simulation)，證明輸出的資料速率至少可達到22.72 MHz以上，可符合IEEE 802.16e標準的需求。

　　A single chip of variable length FFT processor is presented in this thesis. This processor can be applied for the applications with 128/256/512/1024/2048-point FFT. This processor is based on SDF (single path delay feedback) pipeline architecture with radix-2^3 computation element. The number of bits for input data and twiddle factors is carefully selected by system simulation to meet the requirements of OFDM system. In addition, we propose a feedback twiddle factor generator to instead the lookup table for twiddle factors to reduce the storage size of memory.
The FFT processor is carried out by CMOS 0.35μm 2P4M process with core area 3.381x3.3625 mm^2. In the gate level simulation, the output data rate of this FFT processor is above 22.72MHz, so the processor can meet the requirement of IEEE 802.16e standard.

誌謝 i
摘要 ii
Abstract iii
圖索引 vi
表索引 viii
第一章　簡介 1
第二章　快速傅立葉轉換演算法及硬體架構 4
2.1　分時、分頻快速傅立葉轉換 4
2.1.1 分時快速傅立葉轉換 4
2.1.2分頻快速傅立葉轉換 7
2.2　Radix-2/4/8 分時快速傅立葉轉換 10
2.3　Radix-23 分時快速傅立葉轉換 15
2.4 Radix-24 分時快速傅立葉轉換 18
2.5 快速傅立葉轉換演算法選擇說明 21
2.5.1 各種FFT演算法所需要的複數乘法器 21
2.6 記憶體式（Memory-based）快速傅立葉轉換架構 26
2.7 管線（Pipeline）快速傅立葉轉換架構 27
2.7.1 Radix-2多路徑換向 27
2.7.2 Radix-2單一路徑延遲迴授 30
2.7.3 硬體架構選擇說明 34
第三章　可變長度快速傅立葉轉換電路設計 35
3.1 基本元件設計 35
3.1.1　Radix-2 單一路徑延遲迴授架構和運算元件 35
3.1.2　乘法器等效元件 36
3.2　128/256/512/1024/2048點可變長度FFT架構 38
3.3　迴授旋轉因子產生器 40
第四章　系統模擬和晶片設計流程 46
4.1 硬體需求 46
4.2　晶片設計流程 50
4.2.1　加入可測試性設計 55
4.2.2　佈局和繞線 57
4.2.3　DRC和LVS驗證 57
4.2.4　Nanosim模擬結果 59
第五章　結論 61
參考文獻 63

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