本論文採用 TSMC.18μm 製程技術，分析管線式類比數位轉換器的架構，設計實做一個12位元，150萬取樣速率且低功率的類比數位轉換器。利用逐次逼近型類比數位轉換器取代傳統以快閃式類比數位轉換器的子類比數位轉換器，提高各管線階級的位元輸出，此大幅減低管線階級數量使得整體電路只使用一個耗能極大的運算放大器。此外，因採用逐次逼近型類比數位轉換器，輸入訊號可達到軌對軌的訊號擺幅，藉此提高類比數位轉換器的精確度，並可取代前端取樣保持電路更進一步降低功率消耗。逐次逼近型類比數位轉換器以非同步方式提高整體類比數位轉換器的轉換速度。並在子類比數位轉換器取樣時期利用一個額外的動態比較器使得管線階級在相同執行時間內多產生一個位元輸出。
使用動態比較器技術來降低整體的功率消耗。同時使用對稱式靴帶式交換器以控制前端取樣開關，進而達到減少低電壓操作時對取樣保持電路線性度的影響。並且結合數位錯誤更正電路以提高比較器偏移電壓的容忍度。運算放大器則使用切換式運算放大器技術，藉此更進一步達到降低功率消耗的期望。

In this thesis, the circuits are designing with TSMC.18μm CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 150MS/s and 12-bits individually. In order to achieve a high speed, low power consumption pipelined ADC. The proposed pipelined stage is replaced Flash ADC by SAR ADC and add an extra comparator to determine one additional bit in sampling phase of pipelined stage. This technique reduces large number of pipelined stage and opamp which is energy-hungry in the pipelined ADC. Second, the SAR ADC provides inherent sample-and-hold mechanism so that the front-end sample-and-hold amplifier circuit is non-need. Third, the SAR ADC can achieve rail-to-rail input signal swing and improve the conversion accuracy rather than Flash ADC.
The dynamic comparator is used for lower power consumption for whole circuit. Furthermore, this pipelined ADC implement under a supply voltage as low as 1.8V. The bootstrapped switch is used for controlling the sampling in the front-end. It can reduce the impacts of linearity for operating under low supply voltage. The operation amplifier implement by the partially switched-opamp technique to reduce more power consumption. Finally, the output codes are translated by digital correction circuit, it enhance the comparators input offset error tolerance.

Chapter 1 Introduction 1
1.1. Motivation 1
1.2. Objective 2
1.3. Thesis Organization 3
Chapter 2 The principle of designing a pipeline ADC 4
2.1. Introduction 4
2.2. KT/C Noise 4
2.3. Switch 7
2.3.1. ON-Resistance 7
2.3.2. Charge Injection 7
2.3.3. Clock Feedthrough 8
2.4. Operational Amplifier 9
2.4.1. DC Gain 9
2.4.2. Bandwidth Requirement 11
2.4.3. An Example: Folded Cascode Amplifier 13
2.5. Comparator 15
2.5.1. Dynamic Comparator 17
2.6. Reference Voltage from Resistor 18
Chapter 3 The implementation of ADC 20
3.1. Booster circuit 23
3.2. BIAS circuit 26
3.3. Switch 34
3.4. Amplifiers 40
3.5. Dynamic Comparator 40
3.6. Successive Approximation ADC 48
Chapter 4 Simulation Result of ADC 56
Chapter 5 Conclusion 60
References 62

[1]. J.Arias, V.Boccuzzi, L.Quintanilla, L.Enriquez, D.Bisbal, M.Banu, and J. Barbolla, “Low Pipeline ADC for Wireless LANs,” IEEE J.Solid-state circuits, vol. 39, pp. 1338-1340, August 2004.
[2]. M. Mohajerin, C. Chen and E. Abdel-Raheem, “A new 12-b 40 ms/s, low-power, low-area pipeline ADC for video analog front ends,” IEEE Pacific Rim Conference, pp.597 – 600, Aug. 2005.
[3]. B.K Ahuja, et al., “A 30 Msample/s 12b 110 mW video analog front end for digital camera,” IEEE International Conference of Solid-State Circuits, Vol.1, pp.438 – 479, Feb. 2002.
[4]. D. Kurose, et al., “55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers,” IEEE Journal of Solid-State Circuits, Vol.41, No.7, pp.1589 – 1595, July. 2006.
[5]. J. Francke, Y. Huazhong and L. Rong, “A 10-Bit, 40 MSamples/s Low Power Pipeline ADC for System-on-a-Chip Digital TV Application,” International Semiconductor Conference, Vol.2, pp.421 – 424, Sept. 2006.
[6]. Trojer, M.; Cleris, M.; Gaier, U.; Hebein, T.; Pridnig, P.; Kuttin, B.; Tschuden, B.; Krassnitzer, C.; Kuttin, C.; Pribyl, W., “A 1.2V 56mW 10 bit 165Ms/s pipeline-ADC for HD-video applications,” Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, pp.270 – 273, Sept. 2008.
[7]. B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill Co.Inc, pp.420 – 421, pp.37 – 39, 2001.
[8]. O.A. Adeniran and A. Demosthenous, “Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs,” European Conference of Circuit Theory and Design, pp.55 – 58, Vol.2, Sept. 2005.
[9]. Y. Chouia, et al., “14 b, 50 MS/s CMOS front-end sample and hold module dedicated to a pipelined ADC,” Midwest Symposium of Circuits and Systems, Vol.1, pp.353 – 361, July. 2004.
[10]. C.J.B. Fayomi, G.W. Roberts, and M. Sawan, “Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization,” IEEE International Symposium of Circuits and Systems, Vol. 3, pp.2200 – 2203, May. 2005.
[11]. T.N. Andersen, et al., “A cost-efficient high-speed 12-bit pipeline ADC in 0.18 μm Digital CMOS,” IEEE Journal of Solid-State Circuits, Vol.40, No.7, pp.1506 – 1513, July. 2005.
[12]. R.J. BAKER, “CMOS CIRCUIT DESIGN, LAYOUT, AND SIMULATION, 2nd,” John Wiley, pp.132 – 135, pp.324, pp.727, pp.787, Oct. 2005.
[13]. S. Mallya and J.H. Nevin, “Design procedures for a fully differential folded-cascode CMOS operational amplifier,” IEEE Journal of Solid-State Circuits, Vol.24, No. 6, pp.1737 – 1740. Dec. 1989.
[14]. L. Sumanen, M. Waltari and K. Halonen, “A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters,” IEEE International Conference of Electronics, Circuits and Systems, Vo.1, pp.32 – 35, Dec. 2000.
[15]. T.B. Cho and P.R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” IEEE Journal of Solid-State Circuits, Vol.30, No. 3, pp.166 – 172, March. 1995.
[16]. M. Waltari and K.A.I. Halonen, “1-V 9-bit pipelined switched-opamp ADC,” IEEE Journal of Solid-State Circuits, Vol.36, No.1, pp.129 – 134, Jan. 2001.
[17]. R.V.D. Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd,” Kluwer Academic Publ, pp.521 – 522, March. 2003.
[18]. S.H. Lewis and P.R. Gray, “A Pipelined 5-Msample/s 9-bit analog-to-digital converter,” IEEE Journal of Solid-State Circuits, Vol.22, No.6, pp.954 – 961, Dec. 1987.
[19]. R. Lotfi, et al., “A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters,” International Symposium of Signals, Circuits and Systems, Vol. 2, pp.377 – 380, July. 2003.
[20]. G.W. Roberts, “Calculating distortion levels in sampled-data circuits using SPICE,” IEEE International Symposium of Circuits and Systems, Vol.3, pp.2059 – 2062. May. 1995.
[21]. M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei, “A pseudo-class-AB telescopic-cascode operational amplifier,” International Symposium of Circuits and Systems, Vol.1, pp.737 – 740, May. 2004
[22]. C. Wulff and C. Ytterdal, “0.8V 1GHz dynamic comparator in digital 90nm CMOS technology,” NORCHIP Conference, 23rd, pp.237 – 240, Nov. 2005.
[23]. J. Wang and Y. Qiu, “Analysis and design of fully differential gain-boosted telescopic cascode opamp,” International Conference of Solid-State and Integrated Circuits Technology, Vol.2, pp.1457 – 1460, Oct. 2004.
[24]. S. Runhua and L. Peng, “A gain-enhanced two-stage fully-differential CMOS op amp with high unity-gain bandwidth,” IEEE International Symposium of Circuits and Systems, vol.2, pp.428 – 431, May. 2002.
[25]. B. Shem-Tov, M. Kozak, and E.G. Friedman, “A high-speed CMOS op-amp design technique using negative Miller capacitance,” IEEE International Conference of Electronics, Circuits and Systems, pp.623 – 626, Dec. 2004.
[26]. L. Sumanen, et al., “CMOS dynamic comparators for pipeline A/D converters,” IEEE International Symposium of Circuits and Systems, Vol.5, pp.157 - 160, May. 2002.
[27]. I. Echere and M. Boris, “A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling,” IEEE Journal of Solid-State Circuits, Vol.42, No.4, pp.748 – 756. April. 2007.
[28]. Gubbins, D.; Bumha Lee; Hanumolu, P.K.; Un-Ku Moon, “A Continuous-time Input Pipeline ADC,” IEEE 2008 Custom Integrated Circuits Conference (CICC), pp.169 – 172. 2008.
[29]. Van de Vel, H.; Buter, B.A.J.; van der Ploeg, H.; Vertregt, M.; Geelen, G.J.G.M.; Paulus, E.J.F.; “A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, Vol.44, No.4, pp.1047 – 1056. April. 2009.
[30]. Lee, K.-H.; Kim, Y.-J.; Kim, K.-S.; Lee, S.-H.; “14 bit 50 ms/s 0.18 μm CMOS pipeline ADC based on digital error calibration,” IEEE Electronics Letters, Vol.45, No.21, pp. 1067 – 1069. 2009.
[31]. Varzaghani, A.; Yang, C.-K.K.; “A 4.8 GS/s 5-bit ADC-Based Receiver with Embedded DFE for Signal Equalization,” IEEE Journal of Solid-State Circuits, Vol.44, No.3, pp. 901 – 915. March. 2009.
[32]. Oliveira, J.; Goes, J.; Figueiredo, M.; Santin, E.; Fernandes, J.; Ferreira, J.; “An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification,” IEEE Transactions on Circuits And Systems—II: Express Briefs, VOL. 57, NO. 2, pp. 105 – 109. February. 2010.
[33]. David A Johns & Ken Martin, “Analog Integrated Circuit Design” John Wiley & Sons, 1997.
[34]. S. Sheikhaei, S. Mirabbasi and A. Ivanov, “A 0.35μm CMOS comparator circuit for high-speed ADC applications,” IEEE International Symposium of Circuits and Systems, Vol. 6, pp.6134 - 6137, May. 2005.
[35]. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang and Ying-Zu Lin, "A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure," IEEE Journal of Solid-State Circuits, vol.45, no.4, pp.731-740, Apr. 2010.
[36]. Y.-H. Kim and S.H. Cho, "A 10-bit 300MSample/s Pipelined ADC using Time-Interleaved SAR ADC for Front-End Stages", IEEE International Symposium of Circuits and Systems, Vol. 3, pp.4041 – 4044, June. 2010.
[37]. M. Furuta, M. Nozawa, and T. Itakura, “A 0.06mm2 8.9b ENOB 40MS/s Pipelined SAR ADC in 65nm CMOS”, IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 382-383.
[38]. Jiaming Lin ; Wenhuan Yu ; Temes, G.C., “Energy-efficient time-interleaved and pipelined SAR ADCs”, IEEE International Symposium of Circuits and Systems, Vol. 24, pp.1452 – 1455, June. 2010.
[39]. Z. Cao, S. Yan, and Y. Li, “A 32mW1.25 GS/s 6 b 2 b/step SAR ADC in 0.13μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 542–543.