本論文提出了一個高調頻範圍，低相位雜訊全積體化除整數之頻率合成器。此頻率合成器採用TSMC 0.18μm 1P6M CMOS製程並操作在1.8V供應電壓之下，主要應用於射頻收發機的前端電路。本論文所提出的頻率合成器包含相頻偵測器(PFD)、電荷幫浦(CP)、低通迴路濾波器(LPF)、壓控振盪器(VCO)、自動選頻器(ABS)、最佳頻道選頻器(OBS)、以及含雙模數前置除頻器(dual-modulus prescaler)之pulse-swallow divider。電路設計中以新的架構來達到較寬的可調頻範圍與低相位雜訊的壓控振盪器效能,利用switched capacitors技術降低VCO gain(KVCO)並能涵蓋原有所需頻帶,使得此頻率合成器能在製程、電壓、以及溫度的變化之下而能正常運作。在自動選頻器部分採用二元搜尋的演算法,減少了電路在選擇VCO子頻帶的選頻時間。KVCO在不同頻帶間之變化量有相當差距,加上欲鎖定的頻率可能被好不同VCO子頻帶所涵蓋,因此自動選頻器所選擇之頻帶未必為最佳解,在此論文中提出一個最佳頻道選頻器來選擇一個涵蓋欲鎖到之頻率且擁有最小KVCO變化量之頻帶,並利用KVCO量化值來調整電荷幫浦的電流值。透過最佳頻道選頻器以及可程式化的電荷幫浦,可以在整個操作頻率範圍維持迴路頻寬和穩定度。

This thesis presents a wide tuning, low phase noise CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is designed using the TSMC 0.18μm CMOS 1P6M technology. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection (ABS), an optimum-band selection (OBS), and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator with switched capacitors technique with a lowered VCO gain (KVCO) to achieve wide tuning range and low phase noise in order to cover the desired operating frequency bands and to accommodate process, voltage, and temperature (PVT) variations. The ABS accomplishes the efficient search for a VCO discrete tuning curve among a group of frequency sub-bands. It is apparent to reduce the calibration time by adopting the binary search algorithm to select the calibration word. However, the variation of Kvco across different channels can still be large after the execution of ABS. There might be many sub-bands covering the desired frequency. Hence the sub-band which is selected by ABS could not be an optimum choice for the minimum Kvco variation. The OBS is proposed to implement an algorithm in order to find the optimum solution which has the minimum Kvco variation and covers the desired frequency. The Kvco variation is quantified by OBS and using this value to adjust the charge pump current. Therefore, Loop bandwidth and stability were maintained across the operating range by using optimum-band selection(OBS) and a programmable charge pump.

CHAPTER 1 INTRODUCTION...........................................1
1.1 Motivation........................................................................1
1.2 Thesis Organization.....................................................3
CHAPTER 2 THE CONCEPTS OF PLL FREQUENCY SYNTHESIZER.....................................................................4
2.1 General Concepts.........................................................4
2.2 Voltage-Controlled Oscillator(VCO)...........................6
2.2.1 Process variation effect on a VCO..........................6
2.2.2 VCO Gain Variation effect on a VCO.......................7
2.2.3 VCO Gain Variation across on a Single Tuning Curve......................................................................................8
2.3 Loop Bandwidth Variations.........................................9
2.3.1 Factors Causing Loop Bandwidth Variations......9
CHAPTER 3 The Proposed Frequency Synthesizer..10
3.1 Introduction..................................................................10
3.2 Phase Frequency Detector (PFD)............................12
3.3 Voltage Controlled Oscillator (VCO)........................13
3.4 Auto Band Selection (ABS)........................................17
3.4.1 Phase Selector........................................................18
3.4.2 Dual-edge PD..........................................................19
3.4.3 4-bit SAR...................................................................20
3.5 Optimum Band Selection(OBS)...............................22
3.5.1 OBS_CLK..................................................................25
3.5.2 High Speed Counter...............................................27
3.6 Charge Pump (CP).....................................................28
3.7 Frequency Divider.......................................................29
3.7.1 Dual-modulus prescaler........................................30
3.8 Loop filter......................................................................32
3.9 Lock Detector...............................................................34
CHAPTER 4 SIMULATION RESULTS............................36
4.1 RF Model and CMOS Process.................................36
4.2 Simulation results of PFD.........................................36
4.3 Simulation results of CP...........................................38
4.4 Simulation results of VCO.........................................39
4.5 Simulation results of ABS.........................................41
4.6 Simulation results of Frequency Synthesizer........41
CHAPTER 5 CONCLUSION AND FUTURE WORK....44
5.1 Conclusion...................................................................44
5.2 Future Work..................................................................45
Reference...........................................................................46

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