隨著可攜式的電子產品的發展越來越頻繁，像是手機、數位相機、PDA…等。各家公司相繼推出各個類型的機種，每個機種都有多樣的功能。其中一項功能-低消耗功率，一直是學術界和業界探討的議題，能找到有效降低晶片的消耗功率將能讓可攜式電子產品向前邁進一大步。由於可攜式電子產品擁有的功能越來越多，加上LCD面板的大小不斷增加，導致功率消耗剖大，因此延長電池的使用壽命將是重要的議題。此外，在製程技術持續地演進，所需的工作電壓也隨著製程的進步而降低，顯示電源管理會直接影響電路的消耗功率。相對於降低整體IC消耗功率和不影響IC效能的前提下，本論文找出關鍵路徑(Critical Path)的演算法，並使用電壓準位調升電路嵌入至一般常用的數位邏輯閘中，讓部分不需使用較大供應電壓的電路使用恰當的供應電壓，藉以達到整體的功率消耗降低。
然而由於製程變異(Inter-Die or Intra-Die)可能改變原本的Cell Delay，使用靜態時序分析找出的Critical Path可能會不準。為了克服這問題，本論文使用統計的方式去做時序分析，找出該Path會成為Critical Path的機率為多少(Path Sensitivity)。最後在透過Cell-Based的方式換成自己設計的邏輯閘來降低功率。

As the mobile electronic products development are more and more popular such as mobile phone, digital camera, PDA…etc. Each of company releases variable kind of mobile products, and every portable machine has plenty of functions. A low power consumption design is a significant issue which academics and engineers concern. It would be a major progress if the approach which can drop off the power consumption successfully. The mobile electronic products have more application programs than before and the size of LCD increases continuously, so that the power consumption becomes large. Therefore, expanding the life of battery would be a significant issue. Besides, the process technology has improved day by day, and it would influence the supply voltage be declined. It represents the power management would influence the power consumption of circuit directly. Comparing to drop down the entire IC power consumption and not to influence the performance of IC, the thesis employs the algorithm that searches the Critical Path and embeds the Level Converter Logic into digital circuit. It can offer the proper supply voltage to circuits which do not want to bigger supply voltage for reduce power consumption.
However, the process variation (Inter-Die or Intra-Die) may transform the original Critical Path, the Critical Path which searches through the static timing analysis would not correct. To conquer this problem, the thesis provides the statistical approach to analysis timing. It would search Path Sensitivity which is exactly equal to the probability that a path is critical. Finally, the logic gate which is designed by us would replace the UMC 90nm standard cell through Cell-Based.

CHAPTER 1 Introduction....................................................1
1.1 Introduction...................................................................1
1.2 Motivation.....................................................................2
1.3 Research Goals and Contribution................................3
1.4 Thesis Organization.....................................................3
CHAPTER 2 Introduction of Static Timing Analysis...........4
2.1 Modeling of CMOS Cells.............................................4
2.2 Propagation Delay.......................................................5
2.3 Slew of a Waveform....................................................6
2.4 Timing Arcs and Unateness........................................7
2.5 Operating Conditions..................................................7
2.6 Critical Path................................................................8
CHAPTER 3 Statistical Static Timing Analysis................11
3.1 Introduction................................................................11
3.2 Obtain Linear Model..................................................12
3.3 Path Delay Distributions Based on Parameter Distributions.....................................................................13
3.4 Perturbation and PDF(Probability Distribution Function)..........................................................................14
3.5 Path Sensitivity..........................................................15
CHAPTER 4: Construct Standard Cell Library................19
4.1 Standard Cell Flow Introduction................................19
4.2 Construct Synopsys Library Model...........................20
4.3 Place & Route Model................................................23
CHAPTER 5: Dynamic Level Converter Logic................25
5.1 Multiple Voltage Techniques.....................................25
5.2 Conventional Level Shifter Circuit.............................26
5.3 Dynamic Logic...........................................................27
5.4 Dynamic Logic Combined Level Shifter.....................28
5.5 Combination of Level Converter................................29
5.6 Simulation Level Converter.......................................31
CHAPTER 6: Mix Design Level Converter Logic and UMC90 nm Standard Cell...............................................34
6.1 New Design Flow for LC logic and Standard Cell.....34
6.2 Compare and Result.................................................36
CHAPTER 7: Conclusion and Future Work....................39
7.1 Conclusion................................................................39
7.2 Future Works............................................................39
References.....................................................................40

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[27] 張裕睿，具有PVT容忍能力之CMOS電壓準位調升電路，國立中正大學電機工
程研究所碩士論文，民國九十四年。