2010年能源國家型科技計畫的主軸專案計劃目標裡，就有提到電力線通訊的發展，由此可見電力線通訊的重要性。由於電力線環境干擾因素多，資料傳輸的過程中容易產生突發性錯誤，因此為了降低錯誤率，本篇論文設計出具有高偵錯能力和糾錯能力的調變/解調晶片應用於電力線通訊中。

設計中應用到了CRC、PWM、FSK、FEC(我們使用binary BCH code)和Interleaving的技術。CRC-16可偵測出資料傳輸的過程中是否發生錯誤，偵錯機率高達99.997%；我們使用BCH code可隨機糾正3位元的錯誤；PWM則根據輸入訊號的1、0，產生不同頻率的數位波。FSK是個頻率調變技術，可利用不同的頻率改變，傳送數位訊息。Interleaving則是將Burst error轉變成 random error。

本設計使用TSMC .18μm 製程，晶片面積1.16毫米平方，使用3.3V/1.8V的供應電壓，消耗功率55.5 μW。

In the 2010, targets of National Science and Technology Program - Energy‘s project plan had mentioned about the development of power line communication (PLC). This shows the importance of PLC. The data transmission occur burst errors easily by the noise interference from the environment. In order to reduce the error rate, we design a modulation/demodulation chip with error correctable and high error detected ability for power line communication in this thesis.
The proposed design consists of Cyclic Redundancy Check (CRC), Pulse Width Modulation (PWM), Frequency Shift Keying (FSK), Forward Error Correction (i.e. binary BCH code), and interleaving techniques. The CRC can detect the errors occurred in the digital communication. The probability of finding error is 99.997%. The BCH code is capable of correcting any combination of 3 or fewer errors in block. The function of PWM is to generate the digital pulses that exhibit the changeable pulse width according to the swing of the input voltage. In the telecommunication, FSK is a frequency modulation scheme such that the digital information can be transmitted through the discrete frequency changes of the carrier. Interleaving can make burst errors look like random errors.
The design is implemented TSMC 0.18μm process. The fabricated chip area is 1.16 millimeter square with 3.3V/1.8V supply voltages. The measured data shows that the proposed design is fully functional and consumes 55.5 μW.

CHAPTER 1 INTRODUCTION....................1
1.1 Motivation............................1
1.2 Research Objectives...................2
1.3 Research Contribution.................3
1.4 Thesis Organization...................4

CHAPTER 2 THE CONCEPTS OF PWM AND FSK.....5
2.1 DSP Controller Circuit................5
2.2 Transmit Protocol.....................7
2.3 Circuit Topologie.....................8
2.4 Pulse Width Modulation................9
2.4.1 Basic Concept.......................9
2.4.2 Circuit Design.....................10
2.5 A Fully Digital FSK Demodulator......12
2.5.1 Basic Concept......................12
2.5.2 Circuit Design.....................13

CHAPTER 3 BASEBAND DESIGN................16
3.1 Interleving Technique................16
3.1.1 Basic Concept......................16
3.1.2 Circuit Design.....................18
3.2 Cyclic Redundancy Check..............19
3.2.1 Basic Concept......................19
3.2.2 UART Format........................20
3.2.3 Circuit Design.....................21

CHAPTER 4 BINARY BCH ENCODER/DECODER.....26
4.1 Binary BCH Overview..................26
4.2 BCH Encoder..........................28
4.3 BCH Decoder..........................30
4.3.1 Basic Concept......................30
4.3.2 Syndrome Computer..................33
4.3.3 Comparison Module..................37

CHAPTER 5 MEASUREMENT RESULT.............40
5.1 Sinulation...........................40
5.1.1 Functional Verification............40
5.1.2 Simulation Result..................41
5.2 Measurement result...................47

CHAPTER 6 CONCLUSION AND FUTURE WORK.....50
6.1 Conclusion...........................50
6.2 Future Work..........................50

Reference................................51

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