中文提要：
本論文為主要分為三部分。第一部分針對互補式金屬氧化物半導體的主動與被動元件原理與特性作說明，對常見的電晶體如雙極性電晶體、金屬氧化物半導體電晶體、異質介面電晶體和假型高速電子移動電晶體作簡介，模擬常見的電阻、電容與電感作結構原理與說明，了解CMOS的主動元件與被動元件的結構與特性有助於微波電路的設計，第二部分說明功率放大器的設計原理與特性，第三部分為設計與模擬兩級串疊式組態A類功率放大器與三級串疊式組態具功率結合之A類功率放大器。

Abstract

Recently, the proliferating needs of high data rate communication systems are increasing the demand for higher frequency bands with broader bandwidth. The K-band (18~26.5 GHz), which include point to point communications (18~23 GHz), ISM band (24 GHz), and automotive radar applications (24 GHz and 22~29 GHz) is one of the most important frequency bands in modern wireless communication systems.
This thesis mainly includes three parts. The first part of the thesis is the introduction to the principles and characteristics for active and passive components of CMOS process and the description of common transistors , such as BJT, CMOSFET, HBT and pHEMT. The principles of resistors, capacitors and inductors in simulations is shown. It is useful for the microwave circuit design to understand the structure and characteristics of active components and passive components in CMOS process. The second part describes the design principles and characteristics of power amplifier. The third part is the design and simulation of the 2 stages cascode configuration Class A power amplifier and the 3 stages cascode configuration Class A power amplifier with power combination.
There are two important scaling trends that are making CMOS increasingly attractive for RF applications. One is the well known dramatic shrinkage of device size, so that transistors in the advanced process generation of CMOS have peak fT values in excess of 55 GHz.The other is the reverse scaling of interconnect. The thicker metal layer and more layers of wiring are enabling the realization of high-quality passive components which are critical for RF circuits. CMOS is the most attractive technology for its low cost, high yield and high level of integration.
However, It is challenging to design a power amplifier with high output power. In the sub-micron CMOS technology, the challenges of CMOS power amplifier design include the low breakdown voltage, low transconductance (gm), and high substrate loss as compared with SiGe HBTs GaAs HBTs and InP-GaAs HBTs technologies. We made efforts in implementing a power amplifier at K-band. The design and simulation of two power amplifier is present. One is the 2 stages power amplifier, the other is the 3 stages power amplifier with power combination. In order to realize the inductive element and capacitive element in sub-milimeter wave or millimeter wave circuit design, the short stub microstrip line and open stub mircrostrip line are used in matching networks between all stages. The cascade configuration is effective structure to minimize Miller effect in high frequency. The peak gain of 2 stages power amplifier is 17 dB at 24 GHz and the saturation output power is 20 dBm. The OP1dB is over 16 dBm. The peak gain of 3 stages power amplifier with power combination is 20 dB at 24 GHz and the saturation output power is 20.5 dBm. The OP1dB is over 15 dBm.The power amplifier with the cascode configuration and power combination techniques is designed and simulated in TSMC 0.18 um CMOS process, which provides deep n-well, and MiM capacitors.

目錄 I
圖表目錄 III
第一章 緒論 1
1.1 前言 1
1.2 研究動機 2
1.3 論文架構 4
第二章 5
2.1 簡介 5
2.2 互補式金屬氧化物電晶體的結構與物理特性 9
2.2.1 電晶體的雜訊來源 9
2.2.2 低摻雜汲級結構(Lower Doped Drain Structure) 9
2.2.3電晶體模型 10
2.2.4 保護環和深層N型井( Guard ring and Deep N-Well ) 14
2.3電阻 16
2.3.1 N型井電阻(N-well resistance) 17
2.3.2 擴散電阻(Diffusion resistance) 17
2.3.3 多晶矽電阻(poly resistance) 18
2.3.4 高多晶矽電阻(High poly resistance) 19
2.4 電容 20
2.4.1金屬氧化物半導體變容器(MOS varactor) 20
2.4.2多晶矽電容(PiP capacitor) 20
2.4.3金屬絕緣層金屬電容(MiM capacitor) 21
2.5電感 24
2.6結語 33
第三章 功率放大器的設計原理與特性 34
3.1簡介 34
3.2 非線性的特性 35
3.2 鄰近通道功率比例(ACPR Adjacent Channel Power Ratio) 40
3.3 誤差向量幅度(EVM Error Vector Magnitude) 41
3.4 負載線法(Load-line method)與負載位移法(Load-pull method) 42
3.5 傳輸線理論 49
3.6 穩定度 53
3.7 功率轉換和匹配網路設計 56
第四章 串疊組態功率放大器 58
4.1 串疊組態 (Cascode configuration) 59
4.2 兩級串疊組態功率放大器 61
4.3 三級串疊組態具功率結合之功率放大器 67
4.4 結語 75
第五章 結論與未來工作 77
參考文獻 82

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