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論文名稱 Title |
一種結構描述語言模擬器的軟體設計 Software Design of an Architecture Description Language Simulator |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
50 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2010-07-29 |
繳交日期 Date of Submission |
2011-02-21 |
關鍵字 Keywords |
模擬器、結構描述語言、剖析器、直譯器、解碼器 Architecture Description Language, simulator, parser, decoder, interpreter |
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統計 Statistics |
本論文已被瀏覽 5657 次,被下載 11 次 The thesis/dissertation has been browsed 5657 times, has been downloaded 11 times. |
中文摘要 |
在系統晶片內,系統結構的設計深深的影響系統的成本、效能與功率,因而需要進行系統結構探索。為了要有效支援結構的探索,所以我們針對現有的結構描述語言在結構敘述能力不足之處,研究出新的結構描述方式,包括多類型的結構樣式敘述與通用的編碼敘述,結合其餘結構敘述方式,形成一種通用性結構敘述語言。 在本研究中,為了支援此通用性結構描述語言的驗證能力,我們設計其模擬器軟體,此模擬器必須能夠支援此結構描述語言的敘述能力,包括:結構式敘述、行為敘述、編碼敘述、通用的各類型結構樣式敘述以及硬體資料結構敘述。針對這些敘述方式,我們在模擬器的軟體設計上,分成幾個軟體模組來實現,包括:模擬器主體設計、通用性的剖析器設計、直譯器設計、通用性的解碼器設計、通用的各類型結構設計與硬體資料結構設計,以達到有效支援此結構敘述語言之模擬驗證的目的。 |
Abstract |
In system-on-chips, system architecture designs greatly affect cost, performance, and power consumption of the systems. In system design time, we thus need to perform system architecture exploration. In order to effectively support architecture exploration, we improve de-efficiency of current architecture description languages and produce new ways of architecture description, including multiple architecture pattern descriptions and generalized coding description. Together with existing architecture description methods, we form a generalized architecture description language. In this thesis research, in order to support verification of designs in the generalized architecture description language, we designed its simulator software. The simulator should support the descriptions of the architecture description language, including structural description, behavioral description, coding description, multiple architecture pattern descriptions, and hardware data structures. We implemented the simulator software in several software modules, including simulator engine, parser design, interpreter design, generalized decoder design, multiple architecture pattern descriptions, and hardware data structures. We thus can effectively support the verification capability of the architecture description language. |
目次 Table of Contents |
目 錄 致謝.............................................................................................................i 摘要............................................................................................................ii Abstract......................................................................................................iii 目錄............................................................................................................iv 圖次............................................................................................................vi 第 一 章 導 論........................................................................................1 1.1 研究動機........................................................................................1 1.2 研究背景........................................................................................2 1.3 問題描述........................................................................................4 1.4 論文組織........................................................................................5 第 二 章 通 用 性 結 構 敘 述 語 言 的 模 擬 器 設計............6 2.1通用性結構敘述語言.....................................................................6 2.2通用性結構敘述語言的模擬器計.................................................9 第 三 章 結 構 描 述 語 言 模 擬 器 的 軟 體 模 組 技術.. ..12 3.1剖析器設計....................................................................................12 3.1.1剖析樹的設計流程.................................................................12 3.1.2字彙分析器.............................................................................13 3.1.3剖析器.....................................................................................14 3.2直譯器設計..........................................................................................17 3.2.1利用堆疊來儲存剖析樹上節點的資訊................................18 3.2.2有限狀態機處理行為建構....................................................18 3.2.3直譯器執行範例....................................................................20 3.3通用性解碼器設計..............................................................................21 3.3.1欄位抓取函式field_get( ).....................................................21 3.3.2欄位放置函式field_put( ).....................................................22 3.3.3欄位比較函式field_compare( )............................................23 3.3.4欄位解碼函式field_decode( )...............................................24 3.3.5欄位解碼範例........................................................................25 3.4基本模組設計………………………………………………………..26 3.4.1 SystemC軟體介紹 …………………………………………26 3.4.2基本模組………..…………………………………………...27 第 四 章 實 作 與 範 例…………………………………………….33 4.1系統實作………………………………………………………33 4.2設計範例………………………………………………………35 第 五 章 結 論......................................................................................38 參考文獻....................................................................................................39 |
參考文獻 References |
[1] 王駿發,等, 系統單晶片概論 SOC, McGraw-Hill, 2006. [2] D A. Patterson and J L. Hennessy, Computer Architecture - A Quantitative Approach, Morgan Kaufmann Publishers, 2008. [3] Prabhat Mishra, et al., “Architecture Description Language (ADL)-Driven Software Toolkit Generation for Architectural Exploration of Programmable SOCs,” ACM Transactions on Design Automation of Electronic Systems, Vol. 11, No. 3, July 2006. [4] Tzen-Jay Txen, ADL-Based Design and Generation of an ARM, Master Thesis, Department of Electrical Engineering, National Cheng Kung University, Taiwan, Taiwan, 2008. [5] P. Marwedel, Matching System and Component Behaviour in MIMOLA Synthesis Tools, Universitat Dortmund D-4600 Dortmund 50, W.-Germany December 10, 1989 [6] George Hadjiyiannis, et al., ISDL: An Instruction Set Description Language for Retargetability, Department of EECS, MIT. [7] Ashok Halambi, et al., EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability, Department of Information and Computer Science University of California, Irvine, CA 92697-3425, USA. [8] Stefan Pees, et al., LISA-Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures, Integrated Signal Processing Systems Aachen University of Technology Aachen, Germany. [9] Li-Feng Lin, Integrating ADL-family Languages into Machine Description of GCC for Reconfigurable Processor Core, Master Thesis, Department of Computing Science, National, National Tsing Hua University, 2004. [10] Chulho Shin, et al., Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications verlag, Springer Verlas, 2007. [11] Tsung Lee, The Design of an Architecture Description Language, Internal Memo, Computing system Lab, Dept. of Electrical Eng., Nat’l Sun Yat-Sen Univ., July 2010. [12] J R. Levine, et al., lex & yacc, O’REILLY, 1992. [13] 侯捷, STL原碼剖析, ??峯, 2002. |
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