這篇論文設計了一個有指令平行效益的SIMD處理器在通用計算的嵌入式系統上，這些嵌入式系統的硬體規模常小於目前被廣泛應用的CPU或是GPU。而我們在此篇論文中，研發了需多技巧去改進我們SIMD處理器的指令編排的時間。藉由應用一些分支界定法來改善我們原本已有的SIMD架構，使之保有優化。這些方法包含PRSR，memorization和 register grouping. 我們另外提供了啟發式方法(heuristic)，這是一種快捷方法可以快速且高效率的改進我們的全面式搜尋，例如 unrolling optimization，instruction distribution，和sign constraint。

透過暫存器包裝和迴圈地展開，我們將SIMD處理器應用在Mibench上並已具有可與VLIW 處理器兼容的效能。而且，我們的暫存器包裝允許處理向量形式的載入或儲存的指令從靜態隨機存取記憶體。這些記憶體存取指令頻繁發生於程式執行的過程，且在我們的SIMD處理器上對指令編排上有著顯著的加速。

This thesis designed an instruction-level-parallelism processor for the embedded system with general purpose computations. The hardware of the embedded system is small-scalar then currently popular CPU or GPU. We exploit some techniques to enhance the instruction scheduling time of our SIMD processor.

By applying branch-and-bound ways to modify algorithm that maintain optimality includes PRSR (pseudo random shift register), memorization, and register grouping. And we also support heuristic ways that is a mental shortcut that allow us to solve exhaustive searching quickly and efficiently such as unrolling optimization, instruction distribution, and sign constraint.

Through register packing and loop unrolling, we applied our SIMD processor on Mibench and have a compatible performance with VLIW processor; moreover, our register packing allows for a vector-wide load from the SRAM. Such a load is a natural fit to a SIMD and achieves significant speedups, when our allocator is used.

論文審定書......................................................................................................i
中文摘要.........................................................................................................iii
英文摘要.........................................................................................................iv
1 Introduction....................................................................................... ......1
1.1 Motivation and Goal..........................................................................1
1.2 A Summary of Our Contribution.........................................................6
1.3 The key Process of Our Methodology...............................................16
2 Related Work.........................................................................................20
2.1 Basic of DFG construction.............................................................. 20
2.1.1 Super-Blocking...................................................................... 20
2.1.2 Loop Unrolling........................................................................ 24
2.2 Instruction Scheduling.....................................................................29
2.2.1 SISD (superscalar)-List Scheduling.......................................... 29
2.2.2 MIMD (VLIW)-Exhaustive Searching.........................................30
2.2.3 SIMD (vector)-A Survey of Approaches................................ .....31
3 Methodology.......................................................................................... 47
3.1 Algorithm Modification that Maintain Optimality................................. 47
3.1.1 PRSR....................................................................................48
3.1.2 Memorization.........................................................................51
3.1.3 Register Grouping...................................................................54
3.2 Heuristics...................................................................................... 59
3.2.1 Unrolling Optimization ............................................................ 60
3.2.2 Instructions Distribution.......................................................... 62
3.2.3 Sign Constraint...................................................................... 65
4 Performance Comparison and Result....................................................... 71
5 Conclusion............................................................................................ 76
6 References............................................................................................ 77

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