本論文主要是提出和探討具有新型額外本體區之無電容式動態隨機存取記憶體之電性特性與記憶體性能表現。有鑑於傳統無電容式動態隨機存取記憶體在面對微縮時的缺點，例如電荷儲存區太小、複雜且無法自我對齊的製作過程、漏電流太大、自我加熱效應太嚴重和字元線/位元線的干擾太明顯，所以我們提出多種具有額外本體結構之無電容式動態隨機存取記憶體，其中兩種元件不但保有平面式溝槽式架構之無電容式動態隨機存取記憶體的優點，像是在同樣元件面積下增加額外的電荷儲存區，和延續將元件操作區和儲存區分隔的概念，還可以有利用額外本體區與源汲極相對位置的改變讓元件具有多功能的特性;，其結構特徵和電性如下： 一、具有額外溝槽式本體架構之垂直式無電容式動態隨機存取記憶體；此結構改良自傳統具有溝槽式架構之平面式無電容式動態隨機存取記憶體，其垂直式通道架構可以有效降低短通道效應。根據模擬結果，我們發現額外溝槽本體不僅能利用自我對齊製程來製作，更因為額外溝槽本體能提供更多的電荷儲存區域以達到扭結效應，且不會讓電洞立即複合，藉此來提升資料保存時間。在記憶體特性表現上，此架構並沒有因為加深的溝槽區而需要更多的寫入時間。因為此架構其汲極電場的延伸方向和溝槽一致，對於資料的寫入速度和傳統平面式溝槽元件相比可以有大幅度的提升，讓元件可以在6奈秒以內完成寫入操作。在最佳化溝槽深度後，元件的扭結效應也得到了一個顯著的提升並加大可程式規劃窗(programming window)，最後在元件的資料保存時間(retention time)表現上和傳統垂直式元件相比進步了794倍。另外，此結構可以因應源汲極與額外溝槽式本體的相對位置來決定要應用為高性能元件或是無電容式動態隨機存取記憶體。當此架構應用為高性能元件時，浮體效應將會被抑制，也會有較低的汲極引致能障穿隧和次臨界擺幅特性。這樣擁有多功能特性的元件在未來將具有很大的潛力可以應用在記憶體處理器上，進一步提升記憶體處理器的集積密度。 二、具有垂直式奈米柱通道架構和不同寬度之額外溝槽式本體架構之無電容式動態隨機存取記憶體；此結構係利用一自我對齊製程結合垂直式奈米柱本體和溝槽式額外本體架構在同一元件中。這個元件可以進一步改善傳統無電容式動態隨機存取記憶體面積的微縮問題，利用現有CMOS技術達到4 F2的元件面積。根據模擬結果，本架構可以利用較低的寫入偏壓來進入寫入的動作，並在1.17奈秒完成操作。接著，可以藉由加大溝槽寬度來提升感應電流窗的大小。藉著使用垂直式奈米柱本體和溝槽式額外本體架構在同一元件中，載子的復合速率可以被降低，讓本架構得到接近0.65秒的資料保存時間，和傳統相比進步了約2 × 105 倍。還有，當面對來自共享字元線/位元線的干擾時，本架構資料保存時間特性的衰退幅度和傳統元件的表現相比進步了33%。另外，當元件操作在高溫時，因為有額外溝槽本體幫助散熱，使元件在感應電流窗部分僅有34.85%的衰退，增加元件熱穩定性的表現。 三、具有電流橋通道之無電容式動態隨機存取記憶體；我們提出並製作利用類似無接面通道與接面負重疊區域的無電容式動態隨機存取記憶體。此架構之製作過程完全匹配現在CMOS技術。在寫入操作時利用空乏區排斥正電荷之概念將正電荷儲存在靠近汲極端之接面負重疊區域中，這讓元件在室溫操作時達到4秒左右的資料保存時間，這樣的表現和國際半導體藍圖的規格相比進步了62.5倍。另外，因為無接面式通道架構的元件其載子移動率對溫度的變化和傳統元件相比有較低的依賴性。所以當元件操作在85℃時，大部分傳統無電容式動態隨機存取記憶體僅可保有1%以下的資料保存時間特性，本架構卻可以保有26%的資料保存時間特性。

This thesis is mainly proposed and discussed the characteristics of novel capacitor-less one-transistor dynamic random access transistor (1T-DRAM) with additional pseudo-neutral body region. Because of the shortcoming of the scaled conventional 1T-DRAM, like reduced charge storage region, complex and non-self-aligned fabrication process, leakage current, self-heating effects, and line disturbance issues etc.. Thus, we propose three kinds of novel 1T-DRAM with additional pseudo-neutral body region and maintain the advantages of the trenched body in the planar device in the following, such as the extra charge storage region without additional area cost, and the separated device operation region and charge storage region for reducing the off-state leakage current and improving the transient characteristics, indicating to improve the critical issues of conventional 1T-DRAM mentioned above. 1. We propose the novel vertical silicon-on-insulator (VSOI)-based 1T-DRAM with trenched body. This proposed device is demonstrated to enhance the kink effect, which ensures the floating body effects, comparing with the conventional device. As for the 1T-DRAM memory characteristics, the proposed device receive a wide programming window and long retention time along with a high-speed “1” and “0” state programming operation. Moreover, the multi-functional behavior allows the device to serve in process-in-memory architecture with highly scalability. 2. We propose a one-transistor dynamic random access memory (1T-DRAM) based on a novel surrounding-gate transistor with wide trenched body (WT-SGT). This 1T-DRAM exhibits favorable transient performance after word/bit line disturbance, which is verified by using Sentaurus TCAD 12.0. The proposed memory cell can be fabricated with a feature area of 4 F2 and with processes that are fully compatible with conventional CMOS technology. This proposed structure also improves the transient performance with good thermal stability and disturbance immunity. 3. Finally, we propose a new 1T-DRAM with an electron-bridge channel structure. This structure built upon bulk substrate can lower the fabrication cost. The wide underlap region enlarge the charge storage region. Also, this region is isolated by the gate/drain depletion region during the programming and read “1” operations. This allows the device to achieve a 4-second-long retention time at room temperature. The carrier mobility of the electron-bridge 1T-DRAM also exhibits reduced dependence on temperature, so that the programming window remains viable at high temperature, while also maintaining 26% of the retention performance when operated at 358 K.

Contents
Thesis Verification Letter……………………………………………….i
Abstract (in Chinese)…………………………………………...………ii
Abstract (in English)…………………………………………………...iv
Contents………………….……………………………………………vi
Figure Captions…………………………………………………...........x
Table Captions…………………………………………………..........xix

Chapter 1 Introduction 1
1.1 Background 1
1.2 Floating-Body Mechanism in SOI MOSFETs 3
1.2.1 Kink Effect 3
1.2.2 Hysteresis and Latch 4
1.2.3 Parasitic Bipolar Transistor Effect 4
1.2.4 Transient and History Effect 4
1.3 The Capacitor-less DRAM Trend 5
1.3.1 CDRAM Basics 5
1.3.1.1 Program, Erase, and Read Operation 5
1.3.2 Capacitor-less One-Transistor DRAM 6
1.3.2.1 Operation Principle 6
1.3.2.1.1 Program by Impact Ionization 6
1.3.2.1.2 Program by Band-to-Band Tunneling 7
1.3.2.1.3 Program by Bipolar Effect 7
1.3.2.1.4 Erase Method 8
1.3.3 A-RAM and A2RAM 8
1.3.4 Multiple Gates Capacitor-less DRAM 9
1.3.4.1 Double-gate FinFET 9
1.3.4.2 Surrounding-gate devices 10
1.4 Overview of the Dissertation 10
Chapter 2 Capacitor-less vertical SOI-based one-transistor DRAM using trench-body structure 22
2.1 Introduction 22
2.2 Device Fabrication and Simulation Condition 23
2.3 Electrical and Transient Characteristics 25
2.4 Conclusion 29
Chapter 3 Multi-function Behavior of a Vertical SOI-based MOSFET with Trench Body Structure and New Erase Mechanism for Use in 1T-DRAM 44
3.1 Introduction 44
3.2 Device Fabrication and Simulation Condition 46
3.3 Electrical and Transient Characteristics 48
3.4 Thermal Analysis 51
3.5 Conclusion 53
Chapter 4 Transient and Thermal Analysis of the Effect of 4 F2 Surrounding Gate 1T-DRAM with Wide Trenched Body on Disturbance Immunity 68
4.1 Introduction 68
4.2 Design Fabrication and Simulation Condition 69
4.3 Electrical and Transient Characteristics 70
4.4 Thermal Analysis 72
4.5 Disturbance Analysis 74
4.6 Conclusion 76
Chapter 5 Enhanced Retention Time and Thermal Stability of a New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage 97
5.1 Introduction 97
5.2 Device Fabrication 98
5.3 Electrical and Transient Characteristics 99
5.4 Conclusion 101
Chapter 6 Conclusion and Future Work 110
6.1 Conclusion 110
6.2 Future work 112
Reference 114
Vita........... 123
Publication List 124

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