隨著系統晶片的時代來臨，單一晶片所包含的元件數越來越多，如何有效率地取得晶片內部的訊號來幫助設計者進行驗證和除錯已成為一個重要的議題和挑戰。而匯流排訊號追蹤是個常見的方法，但是在系統晶片中由於高速的運作時脈，使得所要追蹤的資訊變的相當龐大，所以在擷取資料的過程中必須有效率的將訊號做壓縮以減少輸出的資料量。有鑒於此，在本論文中提出一個硬體的多重解析匯流排資料追蹤器來解決上述的問題。使用者可以依據需求的不同在程式執行的過程中動態改變追蹤訊號的精準度並進一步的針對這些擷取到的訊號進行有效率的壓縮。透過實驗分析的結果，在正向追蹤的模式下平均可達到85%的壓縮率，至於逆向追蹤的模式平均也可達到84%的壓縮率。在軟體方面，我們提出的追蹤資料分析器不但可以把解還原的訊號轉換成Value Change Dump (VCD) 檔案格式，也會進一步的針對追蹤到的訊號進行一些基本的分析並以圖形界介面的方式呈現給使用者觀察。最後，本Intelligent Property (IP) 也順利的整合至一個實際的平台: 3D圖形加速器，並成功 ape-out為晶片。因此，透過多重解析匯流排資料追蹤分析器可以有效的提升系統的除錯能力。

In the System on a Chip () era, more components are embedded in one chip. Therefore, it has been an important issue to assist verification and debugging by observing the signals inside of a chip. The bus signals tracing is a general method to resolve it. However, the quantities of signals that have to be traced in an are very huge, we must to reduce the trace data as more as possible. Because of the reasons described as above, we propose a hardware called multi-resolution bus tracer to overcome these problems in this thesis. In the bus tracer, user can changes the observed accuracy of tracing signals dynamically during the program execution, and reduces all those signals efficiently. The experiment results show that bus tracer can achieve 85% average compressed ratio on the forward tracing, and 84% average compressed ratio on the backward tracing. In the other hand, the software called trace data analyzer not only transfers the trace signals into Value Change Dump (VCD) file format but also provides some essential analyses for user observation. Finally, our IP (Intelligent Property) has been integrated into a real platform: 3D Graphics Acceleration, and tape-out successfully. Therefore, using the multi-resolution bus trace analyzer can promote the abilities of system debugging efficiently.

CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 RESEARCH METHODOLOGY 3
CHAPTER 2 RELATED WORK 5
2.1 AMBA 2.0 (ADVANCED MICROCONTROLLER BUS ARCHITECTURE) 5
2.2 MONITOR TECHNOLOGY 7
2.2.1 BDU (Breakpoint Detection Unit) 7
2.2.2 MAMon 8
2.2.3 AHB Trace Buffer 10
2.2.4 Monitor-Based Test 12
2.2.5 AMBA Navigator 13
2.3 COMPRESSION TECHNOLOGIES 15
2.3.1 Packed Differential Address and Time Stamp (PDATS) 15
2.3.2 Locality-Based Online Trace Compression (LBTC) 18
2.3.3 TCgen 20
2.4 ARM ETM 23
2.5 LOSSLESS COMPRESSION ALGORITHM 23
CHAPTER 3 MULTI-RESOLUTION AMBA TRACER 25
3.1 MAIN PRINCIPLE OF MULTI-RESOLUTION AMBA TRACER 25
3.2 HARDWARE IMPLEMENTATION OF MULTI-RESOLUTION AMBA TRACER 27
3.2.1 Abstraction Module 27
3.2.1.1 Bus Signals Classification 28
3.2.1.2 Bus Signals Abstraction 28
3.2.1.3 Application of Different Abstraction Modes 31
3.2.2 Reduction Module 36
3.2.2.1 ADDR Reducing 36
3.2.2.2 Data Address and Data Value 41
3.2.2.3 Access Control Signals (ACS) 43
3.2.2.4 Protocol Control Signals (PCS) 45
3.2.3 Packing Module and FIFO Module 46
3.2.4 Dynamic Mode Switch 48
3.2.5 Trace Data Stored in On-Chip Memory 51
3.3 DFT (DESIGN FOR TESTABILITY) 52
3.3.1 Build-in Self Test (BIST) 53
3.3.2 Internal Scan Chain 54
3.4 SUMMARY 55
CHAPTER 4 BACKWARD AMBA TRACER 56
4.1 MOTIVATION OF BACKWARD AMBA TRACER 57
4.2 HARDWARE ARCHITECTURE OF BACKWARD AMBA TRACER 62
4.2.1 Periodical Triggering Module 62
4.2.2 Ping-Pong Controller Module 64
4.2.3 HPT (Header Position Table) Module 66
4.3 SUMMARY 67
CHAPTER 5 TRACE DATA ANALYZER 68
5.1 DECOMPRESSION 68
5.1.1 Trace Data Reordering Phase 68
5.1.2 Unpacking Phase 69
5.1.3 Program Address Recovering Phase 71
5.2 VCD (VALUE CHANGE DUMP) FORMAT CONVERTING 72
5.2.1 VCD file format 72
5.2.1.1 Syntax of the VCD file 72
5.2.1.2 Description of keyword commands 73
5.2.1.3 Example of VCD file format 77
5.2.2 Converting Trace Data to VCD File 78
5.3 TRACE DATA ANALYSIS 80
5.4 TRACE MODE CONVERTING 83
5.5 DEVICE DRIVER 84
5.6 SUMMARY 86
CHAPTER 6 VERIFICATION AND TESTING 88
6.1 RTL VERIFICATION 88
6.1.1 Coding Style Checking 88
6.1.2 Code Coverage Analysis 90
6.1.3 Automatic Verification 91
6.1.3.1 RTL Verification Environment 91
6.1.3.2 Auto-Verification Method 92
6.2 GATE LEVEL VERIFICATION 93
6.3 FPGA LEVEL VERIFICATION 94
6.4 CHIP TESTING 96
CHAPTER 7 EXPERIMENTAL RESULTS 98
7.1 COMPRESSION RATIO ANALYSIS 98
7.1.1 Compression Ratio Analysis of Forward Tracing 100
7.1.2 Compression Ratio Analysis of Backward Tracing 103
7.2 ANALYSIS OF TRACE DEPTH ON A TRACE MEMORY 105
7.2.1 Trace Depth of Forward Tracing on Different Memory Size 105
7.2.2 Trace Depth of Backward Tracing on Different Memory Size 107
7.2.3 Comparison of Trace Depth between Forward and Backwad Trace 112
7.3 HARDWARE SYNTHESIS 113
7.4 ADDITIONAL HARDWARE COST ANALYSIS OF BACKWARD TRACING 114
CHAPTER 8 CASE STUDY: 3D GRAPHICS ACCELERATION 117
8.1 THE 3D GRAPHICS ACCELERATION 117
8.2 3D INTEGRATION ENVIRONMENT 118
8.3 THE COMPRESSION RATIO ANALYSIS OF 3D GRAPHIC ACCELERATION 120
8.3.1 Forward Compression Ratio Analysis of 3D Graphic Acceleration 121
8.3.2 Backward Compression Ratio Analysis of 3D Graphics Acceleration 121
8.4 THE BUS TRACER APPLICATION ON 3D GRAPHICS ACCELERATION 124
8.4.1 Application of Forward Tracing on 3D Graphics Acceleration 124
8.4.2 Application of Backward Tracing on 3D Graphic Acceleration 130
CHAPTER 9 CONCLUSION 133
CHAPTER 10 FUTURE WORK 135
REFERENCES 137
APPENDIX A: CONTROL REGISTERS 139
A.1 TRACE CONTROL REGISTER 140
A.2 DICTIONARY REGISTER 142
APPENDIX B: HARDWARE MODIFICATION OF CHANGING CONFIGURATION 143
B.1 MODIFICATION FOR DIFFERENCE CONTROL SIGNALS 143
B.2 MODIFICATION FOR THE WIDTH OF DATA VALUE 144
B.3 PERIODICAL TRIGGERING FREQUENCE 144

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